EP7209 Datasheet, PDF (33/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
then allow the DMA address generator to gain con-
trol of the bus, to allow LCD refreshes to continue.
When the CL-PS6700 is ready with the data, it as-
serts the PRDY signal. The EP7209 then arbitrates
for the bus and, once the request is granted, the sus-
pended read cycle is resumed. The EP7209 re-
sumes the cycle by asserting the appropriate chip
select, and data is transferred on the next two
clocks if a word read (one clock if a byte read).
There is no support within the EP7209 for detecting
time-outs. The CL-PS6700 device must be pro-
grammed to force the cycle to be completed (with
invalid data for a read) and then generate an inter-
rupt if a read or write access has timed out (i.e.,
RD_FAIL or WR_FAIL interrupt). The system
software can then determine which access was not
successfully completed by reading the status regis-
ters within the CL-PS6700.
The CL-PS6700 has support for DMA data trans-
fers. However, DMA is supported only by software
emulation because the DMA address generator
built into the EP7209 is dedicated to the LCD con-
troller interface. If DMA is enabled within the CL-
PS6700, it will assert its PDREQ signal to make a
DMA request. This can be connected to one of the
EP7209’s external interrupts and be used to inter-
rupt the CPU so that the software can service the
DMA request under program control.
Each of the CL-PS6700 devices can generate an in-
terrupt PIRQ. The PIRQ output is open drain on the
CL-PS6700 devices, so if there are two CL-PS6700
devices they may be wire OR’ed to the same inter-
rupt which can be connected to one of the
EP7209’s active low external interrupt sources. On
the receipt of an interrupt, the CPU can read the in-
terrupt status registers on the CL-PS6700 devices
to determine the cause of the interrupt.
All transactions are synchronized to the EXPCLK
output from the EP7209 in 18.432 MHz mode or
the external 13 MHz clock. The EXPCLK should
be permanently enabled, by setting the EXCKEN
bit in the SYSCON1 register, when the CL-PS6700
is used. The reason for this is that the PC Card in-
terface and CL-PS6700 internal write buffers need
to be clocked after the EP7209 has completed its
bus cycles.
A GPIO signal from the EP7209 can be connected
to the PSLEEP pin of the CL-PS6700 devices to al-
low them to be put into a power saving state before
the EP7209 enters the Standby State. It is essential
that the software monitor the appropriate status
registers within the CL-PS6700s to ensure that
there are no pending posted bus transactions before
the Standby State is entered. Failure to do this will
result in incomplete PC Card accesses.
3.9 Endianness
The EP7209 uses a Little Endian configuration for
internal registers. However, it is possible to con-
nect the device to a Big Endian external memory
system. The Big-endian/Little-endian bit in the
ARM720T control register sets whether the
EP7209 treats words in memory as being stored in
Big Endian or Little Endian format. Memory is
viewed as a linear collection of bytes numbered up-
wards from zero. Bytes 0 to 3 hold the first stored
word, bytes 4 to 7 the second, and so on. In the Lit-
tle Endian scheme, the lowest numbered byte in a
word is considered to be the least significant byte
of the word and the highest numbered byte is the
most significant. Byte 0 of the memory system
should be connected to data lines 7 through 0
(D[7:0]) in this scheme. In the Big Endian scheme
the most significant byte of a word is stored at the
lowest numbered byte, and the least significant
byte is stored at the highest numbered byte. There-
fore, Byte 0 of the memory system should be con-
nected to data lines 31 through 24 (D[31:24]). Load
and store are the only instructions affected by the
Endianness.
Tables 17 and 18 demonstrate the behavior of the
EP7209 in Big and Little Endian mode, including
the effect of performing non-aligned word access-
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