EP7209 Datasheet, PDF(54/128 Page) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

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EP7209 Datasheet, PDF (54/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

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EP7209

Big Endian Mode

Name

Default

RD/WR

Size

Comments

0x8000.0003

PADR

8 Port A Data Register

0x8000.0002

PBDR

8 Port B Data Register

0x8000.0001

8 Reserved

0x8000.0000

PDDR

8 Port D Data Register

0x8000.0043

PADDR

8 Port A data Direction Register

0x8000.0042

PBDDR

8 Port B Data Direction Register

0x8000.0041

8 Reserved

0x8000.0040

PDDDR

8 Port D Data Direction Register

0x0000.0080

PEDR

3 Port E Data Register

0X8000.0000

PEDDR

3 Port E Data Direction Register

Table 26. EP7209 Internal Registers (Big Endian Mode)

NOTE: The following Register Descriptions refer to Little Endian Mode Only

5.1.1 PADR Port A Data Register

ADDRESS: 0x8000.0000

Values written to this 8-bit read/write register will be output on Port A pins if the corresponding data

direction bits are set high (port output). Values read from this register reflect the external state of Port

A, not necessarily the value written to it. All bits are cleared by a system reset.

5.1.2 PBDR Port B Data Register

ADDRESS: 0x8000.0001

Values written to this 8-bit read/write register will be output on Port B pins if the corresponding data

direction bits are set high (port output). Values read from this register reflect the external state of Port

B, not necessarily the value written to it. All bits are cleared by a system reset.

5.1.3 PDDR Port D Data Register

ADDRESS: 0x8000.0003

Values written to this 8-bit read/write register will be output on Port D pins if the corresponding data

direction bits are set low (port output). Values read from this register reflect the external state of Port

D, not necessarily the value written to it. All bits are cleared by a system reset.

5.1.4 PADDR Port A Data Direction Register

ADDRESS: 0x8000.0040

Bits set in this 8-bit read/write register will select the corresponding pin in Port A to become an output,

clearing a bit sets the pin to input. All bits are cleared by a system reset.

5.1.5 PBDDR Port B Data Direction Register

ADDRESS: 0x8000.0041

Bits set in this 8-bit read/write register will select the corresponding pin in Port B to become an output,

clearing a bit sets the pin to input. All bits are cleared by a system reset.

DS453PP2

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