EP7209 Datasheet, PDF (66/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
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Description
TC1OI: TC1 under flow interrupt. This interrupt becomes active on the next falling edge of the
timer counter 1 clock after the timer counter has under flowed (reached zero). It is cleared by
writing to the TC1EOI location.
TC2OI: TC2 under flow interrupt. This interrupt becomes active on the next falling edge of the
timer counter 2 clock after the timer counter has under flowed (reached zero). It is cleared by
writing to the TC2EOI location.
RTCMI: RTC compare match interrupt. This interrupt becomes active on the next rising edge of
the 1 Hz Real Time Clock (one second later) after the 32-bit time written to the Real Time Clock
match register exactly matches the current time in the RTC. It is cleared by writing to the RTCEOI
location.
TINT: 64 Hz tick interrupt. This interrupt becomes active on every rising edge of the internal
64 Hz clock signal. This 64 Hz clock is derived from the 15-stage ripple counter that divides the
32.768 kHz oscillator input down to 1 Hz for the Real Time Clock. This interrupt is cleared by writ-
ing to the TEOI location.
NOTE: TINT is disabled/turned off during the Standby State.
UTXINT1: Internal UART1 transmit FIFO half-empty interrupt. The function of this interrupt
source depends on whether the UART1 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is
clear in the UART1 bit rate and line control register), this interrupt will be active when there is no
data in the UART1 TX data holding register and be cleared by writing to the UART1 data register.
If the FIFO is enabled this interrupt will be active when the UART1 TX FIFO is half or more empty,
and is cleared by filling the FIFO to at least half full.
URXINT1: Internal UART1 receive FIFO half full interrupt. The function of this interrupt source
depends on whether the UART1 FIFO is enabled. If the FIFO is disabled this interrupt will be
active when there is valid RX data in the UART1 RX data holding register and be cleared by
reading this data. If the FIFO is enabled this interrupt will be active when the UART1 RX FIFO is
half or more full or if the FIFO is non empty and no more characters have been received for a
three character time out period. It is cleared by reading all the data from the RX FIFO.
UMSINT: Internal UART1 modem status changed interrupt. This interrupt will be active if either of
the two modem status lines (CTS or DSR) change state. It is cleared by writing to the UMSEOI
location.
SSEOTI: Synchronous serial interface end of transfer interrupt. This interrupt will be active after a
complete data transfer to and from the external ADC has been completed. It is cleared by read-
ing the ADC data from the SYNCIO register.
Table 32. INTSR1 (cont.)
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