EP7209 Datasheet, PDF (89/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.16.3 DAI Status Register
ADDRESS: 0x8000.2100
The DAI Status Register (DAISR) contains bits which signal FIFO overrun and underrun errors and
FIFO service requests. Each of these conditions signal an interrupt request to the interrupt controller.
The status register also flags when transmit FIFOs are not full, when the receive FIFOs are not empty,
when a FIFO operation is complete, and when the right channel or left channel portion of the codec
is enabled (no interrupt generated).
Bits which cause an interrupt signal the interrupt request as long as the bit is set. Once the bit is
cleared, the interrupt is cleared. Read/write bits are called status bits, read-only bits are called flags.
Status bits are referred to as “sticky” (once set by hardware, they must be cleared by software). Writ-
ing a one to a sticky status bit clears it, writing a zero has no effect. Read-only flags are set and
cleared by hardware, and writes have no effect. Additionally some bits which cause interrupts have
corresponding mask bits in the control register and are indicated in the section headings below. Note
that the user has the ability to mask all DAI interrupts by clearing the DAI bit within the interrupt con-
troller mask register INTMR3.
5.16.3.1 Right Channel Transmit FIFO Service Request Flag (RCTS)
The right channel transmit FIFO service request flag (RCTS) is a read-only bit which is set when the
right channel transmit FIFO is nearly empty and requires service to prevent an underrun. RCTS is set
any time the right channel transmit FIFO has four or fewer entries of valid data (half full or less), and
is cleared when it has five or more entries of valid data. When the RCTS bit is set, an interrupt request
is made unless the right channel transmit FIFO interrupt request mask (RCTM) bit is cleared. After
the CPU fills the FIFO such that four or more locations are filled within the right channel transmit FIFO,
the RCTS flag (and the service request and/or interrupt) is automatically cleared.
5.16.3.2 Right Channel Receive FIFO Service Request Flag (RCRS)
The right channel receive FIFO service request flag (RCRS) is a read-only bit which is set when the
right channel receive FIFO is nearly filled and requires service to prevent an overrun. RCRS is set
any time the right channel receive FIFO has six or more entries of valid data (half full or more), and
cleared when it has five or fewer (less than half full) entries of data. When the RCRS bit is set, an
interrupt request is made unless the right channel receive FIFO interrupt request mask (RCRM) bit is
cleared. After six or more entries are removed from the receive FIFO, the LCRS flag (and the service
request and/or interrupt) is automatically cleared.
5.16.3.3 Left Channel Transmit FIFO Service Request Flag (LCTS)
The left channel transmit FIFO service request flag (LCTS) is a read-only bit which is set when the
left channel transmit FIFO is nearly empty and requires service to prevent an underrun. LCTS is set
any time the left channel transmit FIFO has four or fewer entries of valid data (half full or less), and is
cleared when it has five or more entries of valid data. When the LCTS bit is set, an interrupt request
is made unless the left channel transmit FIFO interrupt request mask (LCTM) bit is cleared. After the
CPU fills the FIFO such that four or more locations are filled within the left channel transmit FIFO, the
LCTS flag (and the service request and/or interrupt) is automatically cleared.
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