EP7209 Datasheet, PDF (80/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
SYNCIO is a 32-bit read/write register. The data written to the SYNCIO register configures the master
only SSI. In default mode, the least significant byte is serialized and transmitted out of the synchro-
nous serial interface1 (i.e., SSI1) to configure an external ADC, MSB first. In extended mode, a vari-
able number of bits are sent from SYNCIO[16:31] as determined by the ADC Configuration Length.
The transfer clock will automatically be started at the programmed frequency and a synchronization
pulse will be issued. The ADCIN pin is sampled on every positive going clock edge (or the falling clock
edge, if ADCCKNSEN in SYSCON3 is set) and the result is shifted in to the SYNCIO read register.
During data transfer, the SSIBUSY bit is set high; at the end of a transfer the SSEOTI interrupt will be
asserted. In order to clear the interrupt the SYNCIO register must be read. The data read from the
SYNCIO register is the last sixteen bits shifted out of the ADC.
The length of the data frame can be programmed by writing to the SYNCIO register. This allows many
different ADCs to be accommodated. The device is SPI/Microwire compatible (transfers are in multi-
ples of 8 bits). However, to be compatible with some non-SPI/Microwire devices, the data written to
the ADC device can be anything between 8 to 16 bits. This is user-definable as defined in the ADC
Configuration Extension section of the SYNCIO register.
Bit
0:7 or 0:6
8:12 or 7:12
13
14
16:31
Description
ADC Configuration Byte: When the ADCCON control bit in the SYSCON3 register = 0, this is
the 8-bit configuration data to be sent to the ADC. When the ADCCON control bit in the
SYSCON3 register = 1, this field determines the length of the ADC configuration data held in the
ADC Configuration Extension field for sending to the ADC.
Frame length: The Frame Length Field is the total number of shift clocks required to complete a
data transfer.
In default mode, MAX148/9 (and for many ADCs), this is 25 = (8 for configuration byte + 1 null bit
+ 16 bits result).
In extended mode, AD7811/12, this is 23 = (10 for configuration byte + 3 null + 10 bits result).
SMCKEN: Setting this bit will enable a free running sample clock at twice the programmed ADC
clock frequency to be output on the SMPLCK pin.
TXFRMEN: Setting this bit will cause an ADC data transfer to be initiated. The value in the ADC
configuration field will be shifted out to the ADC and depending on the frame length programmed,
a number of bits will be captured from the ADC. If the SYNCIO register is written to with the
TXFRMEN bit low, no ADC transfer will take place, but the Frame length and SMCKEN bits will
be affected.
ADC Configuration Extension: When the ADCCON control bit in the SYSCON3 register = 0
this field is ignored for compatibility with the CL-PS7111. When the ADCCON control bit in the
SYSCON3 register = 1, this field is the configuration data to be sent to the ADC. The ADC Con-
figuration Extension field length is determined by the value held in the ADC Configuration Length
field (SYNCIO[6:0]).
Table 47. SYNCIO
5.12 STFCLR Clear all ‘Start Up Reason’ flags location
ADDRESS: 0x8000.05C0
A write to this location will clear all the ‘Start Up Reason’ flags in the system flags status register SYS-
FLG. The ‘Start Up Reason’ flags should first read to determine the reason why the chip was started
(i.e., a new battery was installed). Any value may be written to this location.
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