EP7209 Datasheet, PDF (38/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
3.11.2.1 DAI Operation
Following reset, the DAI logic is disabled. To en-
able the DAI, the applications program should first
clear the emergency underflow and overflow status
bits, which are set following the reset, by writing a
1 to these register bits (in the DAISR register).
Next, the DAI control register should be pro-
grammed with the desired mode of operation using
a word write. The transmit FIFOs can either be
“primed” by writing up to eight 16-bit values each,
or can be filled by the normal interrupt service rou-
tine which handles the DAI FIFOs. Finally, the
FIFOs for each channel must be enabled via writes
to DAIDR2. At this point, transmission/reception
of data begins on the transmit (SDOUT) and re-
ceive (SDIN) pins. This is synchronously con-
trolled by the 9.216 MHz (6.5 MHz in 13 MHz
mode) internal clock or the externally supplied bit
clock (SCLK), and the serial frame clock (LRCK).
3.11.2.2 DAI Frame Format
Each DAI frame is 128 bits long and is comprises
one audio sample. Of this 128-bit frame, only
32 bits are actually used for digital audio data. The
remaining bits are output as zeros. The LRCK sig-
nal is used as a frame synchronization signal. Each
transition of LRCK delineates the left and right
halves of an audio sample. When LRCK transi-
tions from high to low the next 16-bits make up the
left side of an audio sample. When LRCK transi-
tions from low to high the next 16-bits make up the
right side of an audio sample.
3.11.2.3 DAI Signals
MCLK
SCLK
oversampled clock. Used as an in-
put to the EP7209 for generating the
DAI timing. This signal is also usu-
ally used as an input to a DAC/ADC
as an oversampled clock. This sig-
nal is fixed at 256 times the audio
sample frequency.
bit clock. Used as the bit clock input
into the DAC/ADC. This signal is
fixed at 128 times the audio sample
frequency.
LRCK
SDOUT
SDIN
frame sync. Used as a frame syn-
chronization input to the
DAC/ADC. This signal is fixed at
the audio sample frequency. This
signal is clocked out on the negative
going edge of SCLK.
digital audio data out. Used for
sending playback data to a DAC.
This signal is clocked out on the
negative going edge of the SCLK
output.
digital audio input. Used for receiv-
ing record data from an ADC. This
signal is latched by the EP7209 on
the positive going edge of SCLK.
LRCK
SCLK
SDATA O
SDATAI
Left Channel
128 SCLKs
Right Channel
MSB _{-1 -2 -3 -4 -5 +5 +4 +3 +2 +1} LSB
MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB
MSB _{-1 -2 -3 -4 -5 +5 +4 +3 +2 +1} LSB
MSB _{-1 -2 -3 -4 +5 +4 +3 +2 +1} LSB
Figure 8. EP7209 Rev C - Digital Audio Interface Timing – MSB/Left Justified format
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