EP7209 Datasheet, PDF (92/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
Bit
4
5
6
7
8
9
10
11
12
13
14
15
16:31
Description
Right Channel Transmit FIFO Underrun
0 — Right Channel transmit FIFO has not experienced an underrun
1 — Right Channel transmit logic attempted to fetch data from transmit FIFO while it was empty,
request interrupt
RCRO: Right Channel Receive FIFO Overrun
0 — Right Channel receive FIFO has not experienced an overrun
1 — Right Channel receive logic attempted to place data into receive FIFO while it was full,
request interrupt
LCTU: Left Channel Transmit FIFO Underrun
0 — Left Channel transmit FIFO has not experienced an underrun
1 — Left Channel transmit logic attempted to fetch data from transmit FIFO while it was empty,
request interrupt
LCRO: Left Channel Receive FIFO Overrun
0 — Left Channel receive FIFO has not experienced an overrun
1 — Left Channel receive logic attempted to place data into receive FIFO while it was full,
request interrupt
RCNF: Right Channel Transmit FIFO Not Full (read-only)
0 — Right Channel transmit FIFO is full
1 — Right Channel transmit FIFO is not full
RCNE: Right Channel Receive FIFO Not Empty (read-only)
0 — Right Channel receive FIFO is empty
1 — Right Channel receive FIFO is not empty
LCNF: LCNETelecom Transmit FIFO Not Full (read-only)
0 — Left Channel transmit FIFO is full
1 — Left Channel transmit FIFO is not full
LCNE: Left Channel Receive FIFO Not Empty (read-only)
0 — Left Channel receive FIFO is empty
1 — Left Channel receive FIFO is not empty
FIFO: FIFO Operation Completed (read-only)
0 — A FIFO Operation has not completed since the last time this bit was cleared
1 — THe FIFO Operation was completed
Reserved
Reserved
Reserved
Reserved
Table 51. DAI Control, Data and Status Register Locations (cont.)
92
DS453PP2