EP7209 Datasheet, PDF (19/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
• Oscillator and phase locked loop (PLL) to gen-
erate the core clock speeds of 18.432 MHz,
36.864 MHz, 49.152 MHz, and 73.728 MHz
from an external 3.6864 MHz crystal, with an
alternative external clock input (used in
13 MHz mode).
• A low power 32.768 kHz oscillator.
The EP7209 design is optimized for low power dis-
sipation and is fabricated on a fully static
0.25 micron CMOS process. It is available in a
256-ball PBGA or a 208-pin LQFP package.
Figure 2 shows a simplified block diagram of the
EP7209. All external memory and peripheral de-
vices are connected to the 32-bit data bus using the
external 28-bit address bus and control signals.
3.1 CPU Core
The ARM720T consists of an ARM7TDMI 32-bit
RISC processor, a unified cache, and a memory
management unit (MMU). The cache is four-way
set associative with 8-kbytes organized as 512 lines
of 4 words. The cache is directly connected to the
ARM7TDMI, and therefore caches the virtual ad-
dress from the CPU. When the cache misses, the
MMU translates the virtual address into a physical
address. A 64-entry translation lookaside buffer
(TLB) is utilized to speed the address translation
process and reduce bus traffic necessary to read the
page table. The MMU saves power by only trans-
lating the cache misses.
See the ARM720T Data sheet for a complete de-
scription of the various logic blocks that make up
the processor, as well as all internal register infor-
mation.
13-MHZ INPUT
3.6864 MHZ
32.768 KHZ
NPOR, RUN,
RESET, WAKEUP
BATOK, NEXTPWR
PWRFL, BATCHG
EINT[1:3], FIQ,
MEDCHG
FLASHING LED DRIVE
PORTS A, B, D (8-BIT)
PORT E (3-BIT)
KEYBD DRIVERS (0:7)
BUZZER DRIVE
DC-TO-DC
ADCCLK, ADCIN,
ADCOUT, SMPCLK,
ADCCS
SSICLK, SSITXFR,
SSITXDA, SSIRXDA,
SSIRSFR
PLL
32.768-KHZ
OSCILLATOR
STATE CONTROL
POWER
MANAGEMENT
INTERRUPT
CONTROLLER
RTC
GPIO
PWM
SSI1 (ADC)
DAI
SSI2
CODEC
ARM720T
ARM7TDMI
CPU CORE
8-KBYTE
CACHE
MMU
WRITE
BUFFER
TIMER
COUNTERS (2)
ON-CHIP
BOOT ROM
INTERNAL DATA BUS
MEMORY CONTROLLER
CL-PS6700
INTFC.
EXPANSION
CONTROL
INTERNAL ADDRESS BUS
LCD
DMA
ICE-JTAG
LCD
CONTROLLER
ON-CHIP SRAM
38,400 BYTES _IrDA
EPB BRIDGE
EPB BUS
UART1
UART2
D[0:31]
PB[0:1], NCS[4:5]
EXPCLK, WORD, NCS[0:3],
EXPRDY, WRITE
A[0:27],
DRA[0:12]
TEST AND
DEVELOPMENT
LCD DRIVE
LED AND
PHOTODIODE
ASYNC
INTERFACE 1
ASYNC
INTERFACE 2
Figure 2. EP7209 Block Diagram
DS453PP2
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