EP7209 Datasheet, PDF (102/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
6.5 I/O Buffer Characteristics
All I/O buffers on the EP7209 are CMOS threshold
input bidirectional buffers except the oscillator and
power pads. For signals that are nominally inputs,
the output buffer is only enabled during pin test
mode. All output buffers are tristated during system
(hi-Z) test mode. All buffers have a standard
CMOS threshold input stage (apart from the
Schmitt triggered inputs) and CMOS slew rate con-
trolled output stages to reduce system noise.
Table 57 defines the I/O buffer output characteris-
tics which will apply across the full range of tem-
perature and voltage (i.e., these values are for 3.3
V, +70°C).
All propagation delays are specified at 50% V_DD to
50% V_DD, all rise times are specified as 10% V_DD
to 90% V_DD and all fall times are specified as 90%
V_DD to 10% V_DD.
Buffer Type
I/O strength 1
I/O strength 2
Drive Current
±4 mA
±12 mA
Propagation
Delay (Max)
7
5
Rise Time
(Max)
14
6
Table 57. I/O Buffer Output Characteristics
6.6 JTAG Bandary Scan Signal Ordering
Fall Time
(Max)
14
6
Load
50 pF
50 pF
Pin
Signal
No.
Type Strength Reset
State
1
nCS[5]
Out
1
High
2
VDDIO
Pad Pwr
3
VSSIO
Pad Gnd
4
EXPCLK
I/O
1
5
WORD
Out
1
Low
6
WRITE
Out
1
Low
7 RUN/CLKEN
I/O
1
Low
8
EXPRDY
In
1
9
TXD[2]
Out
1
High
10
RXD[2]
In
11
TDI
In
with p/u*
12
VSSIO
Pad Gnd
13
PB[7]
I/O
1
Input
14
PB[6]
I/O
1
Input
15
PB[5]
I/O
1
Input
16
PB[4]
I/O
1
Input
17
PB[3]
I/O
1
Input
18
PB[2]
I/O
1
Input
Table 58. 208-Pin LQFP Numeric Pin Listing
Pin
Signal
No.
Type Strength Reset
State
19
PB[1]/
PRDY2
I/O
1
Input
20
PB[0]/
PRDY1
I/O
1
Input
21
VDDIO
Pad Pwr
22
TDO
Out
1
Tristate
23
PA[7]
I/O
1
Input
24
PA[6]
I/O
1
Input
25
PA[5]
I/O
1
Input
26
PA[4]
I/O
1
Input
27
PA[3]
I/O
1
Input
28
PA[2]
I/O
1
Input
29
PA[1]
I/O
1
Input
30
PA[0]
I/O
1
Input
31
LEDDRV
Out
1
Low
32
TXD[1]
Out
1
High
33
VSSIO
Pad Gnd
1
High
34
PHDIN
In
35
CTS
In
36
RXD[1]
In
Table 58. 208-Pin LQFP Numeric Pin Listing (cont.)
102
DS453PP2