EP7209 Datasheet, PDF(36/128 Page) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

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EP7209 Datasheet, PDF (36/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

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EP7209

3.11.1 Codec Sound Interface

The codec interface allows direct connection of a

telephony type codec to the EP7209. It provides all

the necessary clocks and timing pulses and per-

forms a parallel to serial conversion or vice versa

on the data stream to or from the external codec de-

vice. The interface is full duplex and contains two

separate data FIFOs (16 deep by 8-bits wide, one

for the receive data, another for the transmit data).

Data is transferred to or from the codec at

64 kbits/s. The data is either written to or read from

the appropriate 16 byte FIFO. If enabled, a codec

interrupt (CSINT) will be generated after every

8 bytes are transferred (FIFO half full/empty). This

means the interrupt rate will be every 1 msec, with

a latency of 1 msec.

Transmit and receive modes are enabled by assert-

ing high both the CDENRX and CDENTX codec

enable bits in the SYSCON1 register.

NOTE:

Both the CDENRX and CDENTX enable bits

should be asserted in tandem for data to be

transmitted or received. The reason for this

is that the interrupt generation will occur

1 msec after one of the FIFOs is enabled.

For example: If the receive FIFO gets

enabled first and the transmit FIFO at a later

time, the interrupt will occur 1 msec after the

receive FIFO is enabled. After the first inter-

rupt occurs, the receive FIFO will be half full.

However, it will not be possible to know how

full the transmit FIFO will be since it was

enabled at a later time. Thus, it is possible to

unintentionally overwrite data already in the

transmit FIFO (See Figure 6).

After the CDENRX and CDENTX enable bits get

asserted, the corresponding FIFOs become en-

abled. When both FIFOs are disabled, the FIFO sta-

tus flag CRXFE is set and CTXFF is cleared so that

the FIFOs appear empty. Additionally, if the

CDENTX bit is low, the PCMOUT output is dis-

abled. Asserting either of the two enable bits causes

the sync and interrupt generation logic to become

active; otherwise they are disabled to conserve

power.

CDENRX

CDENTX

CSINT

1 ms

Figure 6. Codec Interrupt Timing

DS453PP2

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