EP7209 Datasheet, PDF (45/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
3.13 Timer Counters
Two identical timer counters are integrated into the
EP7209. These are referred to as TC1 and TC2.
Each timer counter has an associated 16-bit
read/write data register and some control bits in the
system control register. Each counter is loaded with
the value written to the data register immediately.
This value will then be decremented on the second
active clock edge to arrive after the write (i.e., after
the first complete period of the clock). When the
timer counter under flows (i.e., reaches 0), it will
assert its appropriate interrupt. The timer counters
can be read at any time. The clock source and mode
are selectable by writing to various bits in the sys-
tem control register. When run from the internal
PLL, 512 kHz and 2 kHz rates are provided. When
using the 13 MHz external source, the default fre-
quencies will be 541 kHz and 2.115 kHz, respec-
tively. However, only in non-PLL mode, an
optional divide by 26 frequency can be generated
Pixel 1 Pixel 2 Pixel 3 Pixel 4
Gray scale
Gray scale
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
4 Bits per pixel
Pixel 1 Pixel 2 Pixel 3 Pixel 4
Gray scale Gray scale Gray scale Gray scale
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
2 Bits per pixel
Pixel 1 Pixel 2 Pixel 3 Pixel 4
Gray scale Gray scale Gray scale Gray scale
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
1 Bit per pixel
Figure 11. Video Buffer Mapping
DS453PP2
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