EP7209 Datasheet, PDF (88/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.16.2.2 DAI Data Register 1
ADDRESS: 0x8000.2080
31:16
Reserved
31:16
Reserved
15:0
Bottom of Left Channel Receive FIFO
Read Access
15:0
Top of Left Channel Transmit FIFO
Write Access
When DAI Data Register 1 (DAIDR1) is read, the bottom entry of the left channel receive FIFO is ac-
cessed. As data is removed by the DAI’s receive logic from the incoming data frame, it is placed into
the top entry of the left channel receive FIFO and is transferred down an entry at a time until it reaches
the last empty location within the FIFO. Data is removed by reading DAIDR1, which accesses the bot-
tom entry of the left channel FIFO. After DAIDR1 is read, the bottom entry is invalidated, and all re-
maining values within the FIFO automatically transfer down one location.
When DAIDR1 is written, the top-most entry of the left channel transmit FIFO is accessed. After a
write, data is automatically transferred down to the lowest location within the transmit FIFO which
does not already contain valid data. Data is removed from the bottom of the FIFO one value at a time
by the transmit logic. It is then loaded into the correct position within the 64-bit transmit serial shifter
then serially shifted out onto the SDOUT pin.
Table 50 shows DAIDR1. Note that the transmit and receive left channel FIFOs are cleared when the
device is reset, or by writing a zero to DAIEN (DAI disabled). Also, note that writes to reserved bits
are ignored and reads return zeros.
Bit
0:15
16:31
Description
LEFT CHANNEL DATA: Transmit/Receive left channel FIFO Data
Read — Bottom of Left Channel Receive FIFO data
Write — Top of Left Channel Transmit FIFO data
Reserved
Table 50. DAI Data Register 1
5.16.2.3 DAI Data Register 2
ADDRESS: 0x8000.20C0
DAIDR2 contains 21 bits and is used to enable and disable the FIFOs for the left and right channels
of the DAI data stream. The left channel FIFO is enabled by writing 0x000D.C000 and disabled by
writing 0x000D.0000. The right channel FIFO is enabled by writing 0x0011.C000 and disabled by writ-
ing 0x0011.0000. After writing a value to this register, wait until the FIFO operation complete bit
(FIFO) is set in the DAI status register before writing another value to this register.
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