EP7209 Datasheet, PDF (60/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
Bit
7
8
9
12
13
14
Description
SS2RXEN: Receive enable for the synchronous serial interface 2. The receive side of SSI2 will
be disabled until this bit is set. When both SSI2TXEN and SSI2RXEN are disabled, the SSI2
interface will be in a power saving state.
UART2EN: Internal UART2 enable bit. Setting this bit enables the internal UART2.
SS2MAEN: Master mode enable for the synchronous serial interface 2. When low, SSI2 will be
configured for slave mode operation. When high, SSI2 will be configured for master mode opera-
tion. This bit also controls the directionality of the interface pins.
OSTB: This bit (operating system timing bit) is for use only with the 13 MHz clock source mode.
Normally it will be set low, however when set high it will cause a 500 kHz clock to be generated
for the timers instead of the 541 kHz which would normally be available. The divider to generate
this frequency is not clocked when this bit is set low.
CLKENSL: CLKEN select. When low, the CLKEN signal will be output on the RUN/CLKEN pin.
When high, the RUN signal will be output on RUN/CLKEN.
BUZFREQ: The BUZFREQ bit is used to select which hardware source will be used as the
source to drive the buzzer output pin. When BUZFREQ = 0, the buzzer signal generated from the
on-chip timer (TC1) is output. When BUZFREQ = 1, a fixed frequency clock is output (500 Hz
when running from the PLL, 528 Hz in the 13 MHz external clock mode). See the BZMOD and
the BZTOG bits (SYSCON2) for more details.
Table 28. SYSCON2 (cont.)
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