EP7209 Datasheet, PDF (61/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.2.3 SYSCON3 System Control Register 3
ADDRESS: 0x8000eeg.2200
15
Reserved
7
VERSN[2]
Reserved
14
Reserved
6
VERSN[1]
Reserved
13
Reserved
5
VERSN[0]
Reserved
12
Reserved
4
ADCCKNSEN
11
Reserved
3
DAISEL
10
Reserved
2
CLKCTL1
9
DAIEN
1
CLKCTL0
8
FASTWAKE
0
ADCCON
Bit
0
1:2
3
4
5:7
8
9
This register is an extension of SYSCON1 and SYSCON2, containing additional control for the
EP7209. The bits of this third system control register are defined in Table 29.
Description
ADCCON: Determines whether the ADC Configuration Extension field SYNCIO(31:16) is to be
used for ADC configuration data. When this bit = 0 (default state) the ADC Configuration Byte
SYNCIO(7:0) only is used for compatibility with the CL-PS7111. When this bit = 1, the ADC Con-
figuration Extension field in the SYNCIO register is used for ADC Configuration data and the
value in the ADC Configuration Byte (SYNCIO(6:0)) selects the length of the data (8-bit to 16-bit).
CLKCTL(1:0): Determines the frequency of operation of the processor and Wait State scaling.
The table below lists the available options.
CLKCTL(1:0)
Value
00
01
10
11
Processor
Frequency
18.432 MHz
36.864 MHz
49.152 MHz
73.728 MHz
Memory Bus
Frequency
18.432 MHz
36.864 MHz
36.864 MHz
36.864 MHz
Wait State
Scaling
1
2
2
2
NOTE:
To determine the number of wait states programmed refer to Table 36 and Table 37.
When operating at 13 MHz, the CLKCTL[1:0] bits should not be changed from the
default value of ‘00’. Under no circumstances should the CLKCTL bits be changed
using a buffered write.
DAIPSEL: When set selects the DAI Interface. This defaults to either the SSI (i.e., DAISEL bit is
low).
ADCCKNSEN: When set, configuration data is transmitted on ADCOUT at the rising edge of the
ADCCLK, and data is read back on the falling edge on the ADCIN pin. When clear (default), the
opposite edges are used.
VERSN[0:2]: Additional read-only version bits — will read ‘000’.
FASTWAKE: When set, the device will wake from the Standby State within one to two cycles of a
4 kHz clock. This bit is cleared at power up, and thus the device first starts using the default one
to two cycles of the 8 Hz clock.
DAIEN: This bit enables the Digital Audio Interface when set (i.e., when DAIEN is high).
Table 29. SYSCON3
DS453PP2
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