EP7209 Datasheet, PDF (97/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
eXPCLK
nCS[5:0]
tNCSRD
nMOE
A[27:0]
WORD
D[31:0] _{Bus held}
t1
tPCSRD
eXPRDY
t5
t6
NOTES:
1) tnCSRD = 50 ns at 36.864 MHz
70 ns at 18.432 MHz
120 ns at 13.0 MHz
t3 t4
Data in
tADRD
t3 t4
Data in
Maximum values for minimum wait states. This time can be extended by integer multiples of the
clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 1 MHz), by either driving
EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling
edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock
period where EXPRDY is sampled again. EXPCLK need not be referenced when driving
EXPRDY, but is shown for clarity.
2) Consecutive reads with sequential access enabled are identical except that the sequential
access wait state field is used to determine the number of wait states, and no idle cycles are
inserted between successive non-sequential ROM/expansion cycles. This improves perfor-
mance so the SQAEN bit should always be set where possible.
3) tnCSRD = tADRD = tPCSRD
Figure 13. Consecutive Memory Read Cycles with Minimum Wait States
DS453PP2
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