EP7209 Datasheet, PDF (72/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.6 LEDFLSH Register
ADDRESS: 0x8000.22C0
6
Enable
5:2
Duty ratio
1:0
Flash rate
The output is enabled whenever LEDFLSH[6] = 1. When enabled, PDDDR[0] needs to be configured
as an output pin and the bit cleared to ‘0’ (See PDDDR Port D Data Direction Register). When the
LED Flasher is disabled, the pin defaults to being used as Port D bit 0. Thus, this will ensure that the
LED will be off when disabled.
The flash rate is determined by the LEDFLSH[1:0] bits, in the following way:
LEDFLSH[1:0]
00
01
10
11
Flash Period (sec)
1
2
3
4
Table 39. LED Flash Rates
LEDFLSH[5:2]
0000
0001
0010
0011
0100
0101
0110
0111
Duty Ratio
(time on : time off)
01:15
02:14
03:13
04:12
05:11
06:10
07:09
08:08
LEDFLSH[5:2]
1000
1001
1010
1011
1100
1101
1110
1111
Table 40. LED Duty Ratio
Duty Ratio
(time on : time off)
09:07
10:06
11:05
12:04
13:03
14:02
15:01
16:00 (continually on)
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DS453PP2