EP7209 Datasheet, PDF (79/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
Gray Scale Value
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Duty Cycle
0
1/9
1/5
4/15
3/9
2/5
4/9
1/2
1/2
5/9
3/5
6/9
11/15
4/5
8/9
1
% Pixels Lit
0%
11.1 %
20.0 %
26.7 %
33.3 %
40.0 %
44.4 %
50.0 %
50.0 %
55.6 %
60.0 %
66.7 %
73.3 %
80.0 %
88.9 %
100 %
% Step Change
11.1 %
8.9 %
6.7 %
6.6 %
6.7 %
5.4 %
5.6 %
0.0 %
5.6 %
5.4 %
6.7 %
6.6 %
6.7 %
8.9 %
11.1 %
Table 46. Gray Scale Value to Color Mapping
5.10.4 FBADDR LCD Frame Buffer Start Address
ADDRESS: 0x8000.1000
This register contains the start address for the LCD Frame Buffer. It is assumed that the frame buffer
starts at location 0x0000000 within each chip select memory region. Therefore, the value stored with-
in the FBADDR register is only the value of the chip select where the frame buffer is located. On reset,
this will be set to 0xC. The register is 4 bits wide (bits [3:0]). This register must only be reprogrammed
when the LCD is disabled (i.e., setting the LCDEN bit within SYSCON2 low).
5.11 SSI Register
5.11.1 SYNCIO Synchronous Serial ADC Interface Data Register
ADDRESS: a0x8000.0500
31:15
Reserved
In the default mode, the bits in SYNCIO have the following meaning:
14
13
12:8
7:0
TXFRMEN
SMCKEN
Frame length
ADC Configuration Byte
15
Reserved
Whereas in extended mode, the following applies:
14
13
12:7
TXFRMEN
SMCKEN
Frame length
6:0
ADC Configuration Length
NOTE:
ADC Configuration Extension
The frame length in extended mode is 6 bits wide to allow up to 16 write bits, 1 null bit and 16 read bits
(= 33 cycles).
DS453PP2
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