EP7209 Datasheet, PDF (39/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
3.11.3 ADC Interface — Master Mode Only
SSI1 (Synchronous Serial Interface)
The first synchronous serial interface allows inter-
facing to the following peripheral devices:
• In the default mode, the device is compatible
with the MAXIM MAX148/9 in external clock
mode. Similar SPI or Microwire compatible de-
vices can be connected directly to the EP7209.
• In the extended mode and with negative-edge
triggering selected (the ADCCON and ADC-
CKNSEN bits are set, respectively, in the
SYSCON3 register), this device can be inter-
faced to Analog Devices’ AD7811/12 chip us-
ing nADCCS as a common RFS/TFS line.
• Other features of the devices, including power
management, can be utilized by software and
the use of the GPIO pins.
The clock output frequency is programmable and
only active during data transmissions to save pow-
er. There are four output frequencies selectable,
which will be slightly different depending whether
the device is operating in a 13 MHz mode or a
18.432 MHz–73.728 MHz mode (see Table 21).
The required frequency is selected by program-
ming the corresponding bits 16 and 17 in the
SYSCON1 register. The sample clock (SMPCLK)
always runs at twice the frequency of the shift
clock (ADCCLK). The output channel is fed by an
8-bit shift register when the ADCCON bit of
SYSCON3 is clear. When ADCCON is set, up to
16 bits of configuration command can be sent, as
specified in the SYNCIO register. The input chan-
nel is captured by a 16-bit shift register. The clock
and synchronization pulses are activated by a write
to the output shift register. During transfers the
SSIBUSY (synchronous serial interface busy) bit
in the system status flags register is set. When the
transfer is complete and valid data is in the 16-bit
read shift register, the SSEOTI interrupt is asserted
and the SSIBUSY bit is cleared.
An additional sample clock (SMPCLK) can be en-
abled independently and is set at twice the transfer
clock frequency.
This interface has no local buffering capability and
is only intended to be used with low bandwidth in-
terfaces, such as for a touch-screen ADC interface.
3.11.4 Master/Slave SSI2 (Synchronous
Serial Interface 2)
A second SPI/Microwire interface with full mas-
ter/slave capability is provided by the EP7209.
Data rates in slave mode are theoretically up to
512 kbits/s, full duplex, although continuous oper-
ation at this data rate will give an interrupt rate of
2 kHz, which is too fast for many operating sys-
tems. This would require a worst case interrupt re-
sponse time of less than 0.5 msec and would cause
loss of data through TX underruns and RX over-
runs.
SYSCON1
bit 17
0
0
1
1
SYSCON1
bit 16
0
1
0
1
13.0 MHz Operation ADCCLK
Frequency (kHz)
4.2
16.9
67.7
135.4
18.432–73.728 MHz Operation
ADCCLK Frequency (kHz)
4
16
64
128
Table 21. ADC Interface Operation Frequencies
DS453PP2
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