EP7209 Datasheet, PDF(22/128 Page) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

EP7209 Datasheet, PDF (22/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

◁

EP7209

1) Permanently connect the RX pin to one of the

active low external interrupt pins.

2) Ensure that on entry to the Standby State, the

chosen interrupt source is not masked, and

the UART is enabled.

3) Send a preamble that consists of one start bit,

8 bits of zero, and one stop bit. This will

cause the EP7209 to wake and execute the

enabled interrupt vector.

The UART will automatically be re-enabled

when the processor re-enters the Operating State,

and the preamble will be received. Since the

UART was not awake at the start of the pream-

ble, the timing of the sample point will be off-

center during the preamble byte. However, the

next byte transmitted will be correctly aligned.

Thus, the actual first real byte to be received by

the UART will get captured correctly.

3.2.2 Idle State

If in the Operating State, the Idle State can be en-

tered by writing to a special internal memory lo-

cation (HALT) in the EP7209. If an interrupt

occurs, the EP7209 will return immediately back

to the Operating State and execute the next in-

struction. The WAKEUP signal can not be used

to exit the Idle State. It is only used to exit the

Standby State.

In the Idle State, the device functions just like it

does when in the Operating State. However, the

CPU clock is halted while it waits for an event

such as a key press to generate an interrupt. The

PLL (in 18.432â73.728 MHz mode) or the exter-

nal 13 MHz clock source always remains active

in the Idle State.

3.2.3 Keyboard Interrupt

For the case of the keyboard interrupt, the fol-

lowing options are available and are selectable

according to bits 1 and 3 of the SYSCON2 regis-

ter (refer to the SYSCON2 Register Description

for details).

â¢ If the KBWEN bit (SYSCON2 bit 3) is set

low, then a keypress will cause a transition

from a power saving state only if the key-

board interrupt is non-masked (i.e., the inter-

rupt mask register 2 (INTMR2 bit 0) is high).

â¢ When KBWEN is high, a keypress will cause

the device to wake up regardless of the state

of the interrupt mask register. This is called

the âKeyboard Direct Wakeupâ mode. In this

mode, the interrupt request may not get ser-

viced. If the interrupt is masked (i.e., the in-

terrupt mask register 2 (INTMR2 bit 0) is

low), the processor simply starts re-execut-

ing code from where it left off before it en-

tered the power saving state. If the interrupt

is non-masked, then the processor will ser-

vice the interrupt.

â¢ When the KBD6 bit (SYSCON2 bit 1) is low,

all 8 of Port A inputs are ORâed together to

produce the internal wakeup signal and key-

board interrupt request. This is the default re-

set state.

â¢ When the KBD6 bit (SYSCON2 bit 1) is

high, only the lowest 6 bits of Port A are

ORâed together to produce the internal wake-

up signal and keyboard interrupt request. The

two most significant bits of Port A are avail-

able as GPIO when this bit is set high.

In the case where KBWEN is low and the

INTMR2 bit 0 is low, it will only be possible to

wakeup the device by using the external WAKE-

UP pin or another enabled interrupt source. The

keyboard interrupt capability allows an OS to use

either a polled or interrupt-driven keyboard rou-

tine, or a combination of both.

DS453PP2

▷