EP7209 Datasheet, PDF (77/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.10 LCD Registers
5.10.1 LCDCON — The LCD Control Register
ADDRESS: 0x8000.02C0
31
GSMD
30
GSEN
29:25
AC prescale
24:19
Pixel prescale
18:13
Line length
12:0
Video buffer size
The LCD control register is a 32-bit read/write register that controls the size of the LCD screen and
the operating mode of the LCD controller. Refer to the system description of the LCD controller for
more information on video buffer mapping.
The LCDCON register should only be reprogrammed when the LCD controller is disabled.
Bit
0:12
13:18
19:24
Description
Video buffer size: The video buffer size field is a 13-bit field that sets the total number of bits x
128 (quad words) in the video display buffer. This is calculated from the formula:
Video buffer size = (Total bits in video buffer / 128) – 1
i.e., for a 640 x 240 LCD and 4-bits per pixel, the size of the video buffer is equal to
614400 bits.
Video buffer = 640 x 240 x 4=614400 bits
Video buffer size field = (614400 / 128) – 1 = 4799 or 0x12BF hex.
The minimum value allowed is 3 for this bit field.
Line length: The line length field is a 6-bit field that sets the number of pixels in one complete
line. This field is calculated from the formula:
line length = (Number of pixels in line / 16) – 1
i.e., for 640 x 240 LCD Line length = (640 / 16) – 1 = 39 or 0x27 hex.
The minimum value that can be programmed into this register is a 1 (i.e., 0 is not a legal value).
Pixel prescale: The pixel prescale field is a 6-bit field that sets the pixel rate prescale. The pixel
rate is always derived from a 36.864 MHz clock when in PLL mode, and is calculated from the
formula:
Pixel rate (MHz) = 36.864 / (Pixel prescale + 1)
When the EP7209 is operating at 13 MHz, pixel rate is given by the formula:
Pixel rate (MHz) = 13 / (Pixel prescale + 1)
The pixel prescale value can be expressed in terms of the LCD size by the formula:
When the EP7209 is operating @ 18.432 MHz:
Pixel prescale = (36864000 / (Refresh Rate x Total pixels in display)) – 1
When the EP7209 is operating @ 13 MHz:
Pixel prescale = (13000000 / (Refresh Rate x Total pixels in display)) – 1
Refresh Rate is the screen refresh frequency (70 Hz to avoid flicker)
The value should be rounded down to the nearest whole number and zero is illegal and will result
in no pixel clock.
EXAMPLE: For a system being operated in the 18.432–73.728 MHz mode, with a 640 x 240
screen size, and 70 Hz screen refresh rate desired, the LCD Pixel prescale equals
36.864E6/(70 x 640x240) – 1 = 2.428
Rounding 2.428 down to the nearest whole number equals 2.
This gives an actual pixel rate of 36.864E6 / (2+1) = 12.288 MHz
Which gives an actual refresh frequency of 12.288E6/(640x240) = 80 Hz.
NOTE: As the CL[2] low pulse time is doubled after every CL[1] high pulse this refresh fre-
quency is only an approximation, the accurate formula is 12.288E6/((640x240)+120) =
79.937 Hz.
Table 45. LCDCON
DS453PP2
77