EP7209 Datasheet, PDF (47/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
3.15 Dedicated LED Flasher
The LED flasher feature enables an external pin
(PD[0]/LEDFLSH) to be toggled at a programma-
ble rate and duty ratio, with the intention that the
external pin is connected to an LED. This module
is driven from the RTCs 32.768 kHz oscillator and
works in all running modes because no CPU inter-
vention is needed once its rate and duty ratio have
been configured (via the LEDFLSH register). The
LED flash rate period can be programmed for 1, 2,
3, or 4 seconds. The duty ratio can be programmed
such that the mark portion can be 1/16, 2/16, 3/16,
…, 16/16 of the full cycle. The external pin can
provide up to 4 mA of drive current.
3.16 Two PWM Interfaces
Two Pulse Width Modulator (PWM) duty ratio
clock outputs are provided by the EP7209. When
the device is operating from the internal PLL, the
PWM will run at a frequency of 96 kHz. These sig-
nals are intended for use as drives for external DC-
to-DC converters in the Power Supply Unit (PSU)
subsystem. External input pins that would normally
be connected to the output from comparators mon-
itoring the external DC-to-DC converter output are
also used to enable these clocks. These are the
FB[0:1] pins. The duty ratio (and hence PWMs on
time) can be programmed from 1 in 16 to 15 in 16.
The sense of the PWM drive signal (active high or
low) is determined by latching the state of this
drive signal during power on reset (i.e., a pull-up on
the drive signal will result in a active low drive out-
put, and visa versa). This allows either positive or
negative voltages to be generated by the external
DC-to-DC converter. PWMs are disabled by writ-
ing zeros into the drive ratio fields in the PMPCON
Pump Control register.
NOTE:
To maximize power savings, the drive ratio
fields should be used to disable the PWMs,
instead of the FB pins. The clocks that
source the PWMs are disabled when the
drive ratio fields are zeroed.
3.17 Boundary Scan
IEEE 1149.1 compliant JTAG is provided with the
EP7209. Table 22 shows what instructions are sup-
ported in the EP7209.
Instruction
EXTEST
SCAN_N
SAMPLE/PRELOAD
IDCODE
BYPASS
Code
Description
Places the selected
0000 scan chain in test
mode.
Connects the Scan
0010 Path Register between
TDI and TDO
NOTE: This instruc-
tion is included for
0011 product testing only
and should never be
used.
Connects the ID regis-
1110 ter between TDI and
TDO
Connects a 1-bit shift
1111 register bit TDI and
TDO
Table 22. Instructions Supported in JTAG Mode
The INTEST function will not be supported for the
EP7209.
Additional user-defined instructions exist, but
these are not relevant to board-level testing. For
further information please refer to the ARM DDI
0087E ARM720T Data Sheet.
As there are additional scan-chains within the
ARM720T processor, it is necessary to include a
scan-chain select function — shown as SCAN_N
in Table 22. To select a particular scan chain, this
function must be input to the TAP controller, fol-
lowed by the 4-bit scan-chain identification code.
The identification code for the boundary scan chain
is 0011.
Note that it is only necessary to issue the SCAN_N
instruction if the device is already in the JTAG
mode. The boundary scan chain is selected as the
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