EP7209 Datasheet, PDF (29/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
Table 12 summarizes the five external interrupt
sources and the effect they have on the processor
interrupts.
3.6 EP7209 Boot ROM
The 128 bytes of on-chip Boot ROM contain a in-
struction sequence that initializes the device and
then configures UART1 to receive 2048 bytes of
serial data that will then be placed in the on-chip
SRAM. Once the download is complete, execution
jumps to the start of the on-chip SRAM. This
would allow, for example, code to be downloaded
to program system FLASH during a product’s
manufacturing process. See Appendix A: Boot
Code for details of the ROM Boot Code with com-
ments to describe the stages of execution.
Selection of the Boot ROM option is determined by
the state of the nMEDCHG pin during a power on
reset. If nMEDCHG is high while nPOR is active,
then the EP7209 will boot from an external memo-
ry device connected to CS[0] (normal boot mode).
If nMEDCHG is low, then the boot will be from the
on-chip ROM. Note that in both cases, following
the de-assertion of power on reset, the EP7209 will
be in the Standby State and requires a low-to-high
transition on the external WAKEUP pin in order to
actually start the boot sequence.
The effect of booting from the on-chip Boot ROM
is to reverse the decoding for all chip selects inter-
nally. Table 13 shows this decoding. The control
signal for the boot option is latched by nPOR,
which means that the remapping of addresses and
bus widths will continue to apply until nPOR is as-
serted again. After booting from the Boot ROM,
the contents of the Boot ROM can be read back
from address 0x00000000 onwards, and in normal
state of operation the Boot ROM contents can be
read back from address range 0x70000000.
Address Range
0000.0000–0FFF.FFFF
1000.0000–1FFF.FFFF
2000.0000–2FFF.FFFF
3000.0000–3FFF.FFFF
4000.0000–4FFF.FFFF
5000.0000–5FFF.FFFF
6000.0000–6FFF.FFFF
7000.0000–7FFF.FFFF
Chip Select
CS[7]
(Internal only)
CS[6]
(Internal only)
nCS[5]
nCS[4]
nCS[3]
nCS[2]
nCS[1]
nCS[0]
Table 13. Chip Select Address Ranges After Boot From
On-Chip Boot ROM
Interrupt
Pin
nEXTFIQ
nEINT1–2
EINT3
nMEDCHG
Input State
Operating State
Latency
Not deglitched; must be Worst case latency
active for 20 µs to be of 20 µsec
detected
Not deglitched
Worst case latency
of 20 µsec
Not deglitched
Worst case latency
of 20 µsec
Deglitched by 16 kHz
clock; must be active
for at least 125 µs to be
detected
Worst case latency
of 141 µsec
Idle State
Latency
Worst case
20 µsec: if only
single cycle
instructions, less
than 1 µsec
As above
As above
Worst case
80 µsec: if only
single cycle
instructions,
125 µsec
Standby State Latency
Including PLL/osc. settling time, approx.
0.25 sec when FASTWAKE = 0, or
approx. 500 µsec when FASTWAKE = 1,
or = Idle State if in 13 MHz mode with
CLKENSL set
As above
As above
As above (note difference if in 13 MHz
mode with CLKENSL set)
Table 12. External Interrupt Source Latencies
DS453PP2
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