EP7209 Datasheet, PDF (53/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
Address
0x8000.0700
0x8000.0740
0x8000.0780
0x8000.07C0
0x8000.0800
0x8000.0840
0x8000.0880–
0x8000.0FFF
0x8000.1000
0x8000.1100
0x8000.1140
0x8000.1240
0x8000.1280
0x8000.12C0–
0x8000.147F
0x8000.1480
0x8000.14C0
0x8000.1500
0x8000.1600
0x8000.16C0
0x8000.1700
Name
TC2EOI
RTCEOI
UMSEOI
COEOI
HALT
STDBY
Reserved
FBADDR
SYSCON2
SYSFLG2
INTSR2
INTMR2
Reserved
UARTDR2
UBLCR2
SS2DR
SRXEOF
SS2POP
KBDEOI
Default
—
—
—
—
—
—
0xC
0
0
0
0
0
0
0
—
—
—
RD/WR
WR
WR
WR
WR
WR
WR
RW
RW
RD
RD
RW
RW
RW
RW
WR
WR
WR
0x8000.1800
Reserved
—
WR
0x8000.1840–
0x8000.1FFF
Reserved
—
Size
—
—
—
—
—
—
Comments
Write to clear TC2 interrupt
Write to clear RTC match interrupt
Write to clear UART modem status changed
interrupt
Write to clear CODEC sound interrupt
Write to enter the Idle State
Write to enter the Standby State
Write will have no effect, read is undefined
4 LCD frame buffer start address
16 System control register 2
16 System status register 2
24 Interrupt status register 2
16 Interrupt mask register 2
Write will have no effect, read is undefined
16 UART2 Data Register
32 UART2 bit rate and line control register
16 Master/slave SSI2 data Register
— Write to clear RX FIFO overflow flag
— Write to pop SSI2 residual byte into RX FIFO
— Write to clear keyboard interrupt
Do not write to this location. A write will
— cause the processor to go into an unsup-
ported power savings state.
Write will have no effect, read is undefined
Table 25. EP7209 Internal Registers Compatible with CL-PS7111 (Little Endian Mode) (cont.)
DS453PP2
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