EP7209 Datasheet, PDF (55/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.1.6 PDDDR Port D Data Direction Register
ADDRESS: 0x8000.0043
Bits cleared in this 8-bit read/write register will select the corresponding pin in Port D to become an
output, setting a bit sets the pin to input. All bits are cleared by a system reset so that Port D is output
by default.
5.1.7 PEDR Port E Data Register
ADDRESS: 0x8000.0080
Values written to this 3-bit read/write register will be output on Port E pins if the corresponding data
direction bits are set high (port output). Values read from this register reflect the external state of Port
E, not necessarily the value written to it. All bits are cleared by a system reset.
5.1.8 PEDDR Port E Data Direction Register
ADDRESS: 0x8000.00C0
Bits set in this 3-bit read/write register will select the corresponding pin in Port E to become an output,
clearing bit sets the pin to input. All bits are cleared by a system reset so that Port E is input by default.
DS453PP2
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