EP7209 Datasheet, PDF (83/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.15 SS2 Registers
5.15.1 SS2DR Synchronous Serial Interface 2 Data Register
ADDRESS: 0x8000.1500
This is the 16-bit wide data register for the full-duplex master/slave SSI2 synchronous serial interface.
Writing data to this register will initiate a transfer. Writes need to be word writes and the bottom 16
bits are transferred to the TX FIFO. Reads will be 32 bits as well; the low 16 bits contain RX data and
the upper 16-bits should be ignored. Although the interface is byte-oriented, data is written in two
bytes at a time to allow higher bandwidth transfer. It is up to the software to assemble the bytes for
the data stream in an appropriate manner.
All reads/writes to this register must be word reads/writes.
5.15.2 SS2POP Synchronous Serial Interface 2 Pop Residual Byte
ADDRESS: 0x8000.16C0
This is a write-only location which will cause the contents of the RX shift register to be popped into
the RX FIFO, thus enabling a residual byte to be read. The data value written to this register is ig-
nored. This location should be used in conjunction with the RESVAL and RESFRM bits in the
SYSFLG2 register.
5.16 DAI Register Definitions
There are five registers within the DAI Interface, one control register, three data registers, and one
status register. The control register is used to mask or unmask interrupt requests to service the DAI’s
FIFOs, and to select whether an on-chip or off-chip clock is used to drive the bit rate, and to en-
able/disable operation. The first pair of data register addresses the top of the right channel transmit
FIFO and the bottom of the right channel receive FIFO. A read accesses the receive FIFOs, and a
write the transmit FIFOs. Note that these are four physically separate FIFOs to allow full-duplex trans-
mission. The status register contains bits which signal FIFO overrun and underrun errors and transmit
and receive FIFO service requests. Each of these status conditions signal an interrupt request to the
interrupt controller. The status register also flags when the transmit FIFOs are not full when the re-
ceive FIFOs are not empty.
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