EP7209 Datasheet, PDF (82/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.13.5 TC2EOI TC2 End of Interrupt Location
ADDRESS: 0x8000.0700
A write to this location will clear the under flow interrupt generated by TC2.
5.13.6 RTCEOI RTC Match End of Interrupt
ADDRESS: 0x8000.0740
A write to this location will clear the RTC match interrupt
5.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt
ADDRESS: 0x8000.0780
A write to this location will clear the modem status changed interrupt.
5.13.8 COEOI Codec End of Interrupt Location
ADDRESS: 0x8000.07C0
A write to this location clears the sound interrupt (CSINT).
5.13.9 KBDEOI Keyboard End of Interrupt Location
ADDRESS: 0x8000.1700
A write to this location clears the KBDINT keyboard interrupt.
5.13.10 SRXEOF End of Interrupt Location
ADDRESS: 0x8000.1600
A write to this location clears the SSI2 RX FIFO overflow status bit.
5.14 State Control Registers
5.14.1 STDBY Enter the Standby State Location
ADDRESS: 0x8000.0840
A write to this location will put the system into the Standby State by halting the main oscillator. A write
to this location while there is an active interrupt will have no effect.
5.14.2
NOTES: 1) Before entering the Standby State, the LCD Controller should be disabled. The LCD
controller should be enabled on exit from the Standby State.
2) If the EP7209 is attempting to get into the Standby State when there is a pending
interrupt request, it will not enter into the low power mode. The instruction will get
executed, but the processor will ignore the command.
HALT Enter the Idle State Location
ADDRESS: 0x8000.0800
A write to this location will put the system into the Idle State by halting the clock to the processor until
an interrupt is generated. A write to this location while there is an active interrupt will have no effect.
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