EP7209 Datasheet, PDF (65/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.3 Interrupt Registers
5.3.1 INTSR1 Interrupt Status Register 1
ADDRESS: 0x8000.0240
15
SSEOTI
7
EINT3
14
UMSINT
6
EINT2
13
URXINT1
5
EINT1
12
UTXINT1
4
CSINT
11
TINT
3
MCINT
10
RTCMI
2
WEINT
9
TC2OI
1
BLINT
8
TC1OI
0
EXTFIQ
The interrupt status register is a 32-bit read only register. The interrupt status register reflects the cur-
rent state of the first 16 interrupt sources within the EP7209. Each bit is set if the appropriate interrupt
is active. The interrupt assignment is given in Table 32.
Bit
0
1
2
3
4
5
6
7
Description
EXTFIQ: External fast interrupt. This interrupt will be active if the nEXTFIQ input pin is forced low
and is mapped to the FIQ input on the ARM720T processor.
BLINT: Battery low interrupt. This interrupt will be active if no external supply is present (nEXT-
PWR is high) and the battery OK input pin BATOK is forced low. This interrupt is de-glitched with
a 16 kHz clock, so it will only generate an interrupt if it is active for longer than 125 µsec. It is
mapped to the FIQ input on the ARM720T processor and is cleared by writing to the BLEOI loca-
tion.
NOTE: BLINT is disabled during the Standby State.
WEINT: Tick Watch dog expired interrupt. This interrupt will become active on a rising edge of the
periodic 64 Hz tick interrupt clock if the tick interrupt is still active (i.e., if a tick interrupt has not
been serviced for a complete tick period). It is mapped to the FIQ input on the ARM720T proces-
sor and the TEOI location
NOTE: WEINT is disabled during the Standby State.
Watch dog timer tick rate is 64 Hz (in 13 MHz and 73.728–18.432 MHz modes).
Watchdog timer is turned off during the Standby State.
MCINT: Media changed interrupt. This interrupt will be active after a rising edge on the nMED-
CHG input pin has been detected, This input is de-glitched with a 16 kHz clock so it will only gen-
erate an interrupt if it is active for longer than 125 µsec. It is mapped to the FIQ input on the
ARM7TDMI processor and is cleared by writing to the MCEOI location. On power-up, the Media
change pin (nMEDCHG) is used as an input to force the processor to either boot from the internal
Boot ROM, or from external memory. After power-up, the pin can be used as a general purpose
FIQ interrupt pin.
CSINT: Codec sound interrupt, generated when the data FIFO has reached half full or empty
(depending on the interface direction). It is cleared by writing to the COEOI location.
EINT1: External interrupt input 1. This interrupt will be active if the nEINT1 input is active (low) it
is cleared by returning nEINT1 to the passive (high) state.
EINT2: External interrupt input 2. This interrupt will be active if the nEINT2 input is active (low) it
is cleared by returning nEINT2 to the passive (high) state.
EINT3: External interrupt input 3. This interrupt will be active if the EINT3 input is active (high) it
is cleared by returning EINT3 to the passive (low) state.
Table 32. INTSR1
DS453PP2
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