EP7209 Datasheet, PDF (84/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.16.1 DAI Control Register
ADDRESS: 0x8000.2000
31:24
Reserved
23
LBM
22
RCRM
21
RCTM
20
LCRM
19
LCTM
18
Reserved
17
ECS
16
DAIEN
15:0
Reserved
The DAI control register (DAIR) contains eight different bit fields that control various functions within
the DAI interface.
Bit
Description
Reserved
0:15
Must be set to 0x0404
7
Reserved
15
Reserved
DAIEN: DAI Interface Enable
0 — DAI operation disabled, control of the SDIN, SDOUT, SCLKLRCK, and LRCK pins given to
the SSI2/codec/DAI pin mulitiplexing logic to assign I/O pins 60-64 to another block.
16
1 — DAI operation enabled
Note that by default, the SSI/CODEC have precedence over the DAI interface in regard to the
use of the I/O pins. Nevertheless, when Bit 3 (MCPSEL) of register SYSCON3 is set to 1, then
the above mentioned DAI ports are connected to I/O pins 60–64.
17
ECS: External Clock Select selects external MCLK when = 1.
18
Reserved
Must be 0.
LCTM: Left Channel Transmit FIFO Interrupt Mask
0 — Left Channel transmit FIFO half-full or less condition does not generate an interrupt (LCTS
19
bit ignored).
1 — Left Channel transmit FIFO half-full or less condition generates an interrupt (state of LCTS
sent to interrupt controller).
LCRM: Left Channel Receive FIFO Interrupt Mask
0 — Left Channel receive FIFO half-full or more condition does not generate an interrupt (LCRS
20
bit ignored).
1 — Left Channel receive FIFO half-full or more condition generates an interrupt (state of LCRS
sent to interrupt controller).
RCTM: Right Channel Transmit FIFO Interrupt Mask
0 — Right channel transmit FIFO half-full or less condition does not generate an interrupt (RCTS
21
bit ignored).
1 — Right channel transmit FIFO half-full or less condition generates an interrupt (state of RCTS
sent to interrupt controller).
RCRM: Right Channel Receive FIFO Interrupt Mask
0 — Right Channel receive FIFO half-full or more condition does not generate an interrupt
22
(RCRS bit ignored).
1 — Right Channel receive FIFO half-full or more condition generates an interrupt (state of RCRS
sent to interrupt controller).
Table 48. DAI Control Register
84
DS453PP2