EP7209 Datasheet, PDF(40/128 Page) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

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EP7209 Datasheet, PDF (40/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

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EP7209

The interface is fully capable of being clocked at

512 kHz when in slave mode. However, it is antic-

ipated that external hardware will be used to frame

the data into packets. Therefore, although the data

would be transmitted at a rate of 512 kbits/s, the

sustained data rate would in fact only be

85.3 kbits/s (i.e., 1 byte every 750 Âµsec). At this

data rate, the required interrupt rate will be greater

than 1 msec, which is acceptable.

There are separate half-word-wide RX and TX

FIFOs (16 half-words each) and corresponding in-

terrupts which are generated when the FIFOâs are

half-full or half-empty as appropriate. The inter-

rupts are called SS2RX and SS2TX, respectively.

There are five pins to support this SSI port: SSIRX-

DA, SSITXFR, SSICLK, SSITXDA, and SSIRX-

FR. The SSICLK, SSIRXDA, SSIRXFR, and

SSITXFR signals are inputs and the SSITXDA sig-

nal is an output in slave mode. In the master mode,

SSICLK, SSITXDA, SSITXFR, and SSIRXFR are

outputs and SSIRXDA is an input. Master mode is

enabled by writing a one to the SS2MAEN bit

(SYSCON2[9]). When the master/slave SSI is not

required, it can be disabled to save power by writ-

ing a zero to the SS2TXEN and the SS2RXEN bits

(SYSCON2[4] [7]). When set, these two bits inde-

pendently enable the transmit and receive sides of

the interface.

The master/slave SSI is synchronous, full duplex,

and capable of supporting serial data transfers be-

tween two nodes. Although the interface is byte-

oriented, data is loaded in blocks of two bytes at a

time. Each data byte to be transferred is marked by

a frame sync pulse, lasting one clock period, and

located one clock prior to the first bit being trans-

ferred. Direction of the SSI2 ports, in slave and

master mode, is shown in Figure 9.

Data on the link is sent MSB first and coincides

with an appropriate frame sync pulse, of one clock

in duration, located one clock prior to the first data

bit sent (i.e., MSB). It is not possible to send data

LSB first.

When operating in master mode, the clock frequen-

cy is selected to be the same as the ADC interfaceâs

(master mode only SSI1) â that is, the frequencies

are selected by the same bits 16 and 17 of the

SYSCON1 register (i.e., the ADCKSEL bits).

Thus, the maximum frequency in master mode is

128 kbits/s. The interface will support continuous

transmission at this rate assuming that the OS can

respond to the interrupts within 1 msec to prevent

over/underruns.

Slave 7209

SSIRXFR

SSITXFR

SSICLK

SSIRXDA

SSITXDA

Master 7209

SSIRXFR

SSITXFR

SSICLK

SSITXDA

SSIRXDA

Figure 9. SSI2 Port Directions in Slave and Master Mode

DS453PP2

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