EP7209 Datasheet, PDF (30/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
3.7 Memory and I/O Expansion Interface
Six separate linear memory or expansion segments
are decoded by the EP7209, two of which can be re-
served for two PC Card cards, each interfacing to a
separate single CL-PS6700 device. Each segment
is 256 Mbytes in size. Two additional segments
(i.e., in addition to these six) are dedicated to the
on-chip SRAM and the on-chip ROM. The on-chip
ROM space is fully decoded, and the SRAM space
is fully decoded up to the maximum size of the vid-
eo frame buffer programmed in the LCDCON reg-
ister (128 kbytes). Beyond this address range the
SRAM space is not fully decoded (i.e., any access-
es beyond 128 kbyte range get wrapped around to
within 128 kbyte range). Any of the six segments
are configured to interface to a conventional
SRAM-like interface, and can be individually pro-
grammed to be 8-, 16-, or 32-bits wide, to support
page mode access, and to execute from 1 to 8 wait
states for non-sequential accesses and 0 to 3 for
burst mode accesses. The zero wait state sequential
access feature is designed to support burst mode
ROMs. For writable memory devices which use the
nMWE pin, zero wait state sequential accesses are
not permitted and one wait state is the minimum
which should be programmed in the sequential
field of the appropriate MEMCFG register. Bus cy-
cles can also be extended using the EXPRDY input
signal.
Page mode access is accomplished by setting
SQAEN = 1, which enables accesses of the form
one random address followed by three sequential
addresses, etc., while keeping nCS asserted. These
sequential bursts can be up to four words long be-
fore nCS is released to allow DMA and refreshes to
take place. This can significantly improve bus
bandwidth to devices such as ROMs which support
page mode. When SQAEN = 0, all accesses to
memory are by random access without nCS being
de-asserted between accesses. Again nCS is de-as-
serted after four consecutive accesses to allow
DMAS.
Bits 5 and 6 of the SYSCON2 register independent-
ly enable the interfaces to the CL-PS6700 (PC Card
slot drivers). When either of these interfaces are en-
abled, the corresponding chip select (nCS4 and/or
nCS5) becomes dedicated to that CL-PS6700 inter-
face. The state of SYSCON2 bit 5 determines the
function of chip select nCS4 (i.e., CL-PS6700 in-
terface or standard chip select functionality); bit 6
controls nCS5 in a similar way. There is no interac-
tion between these bits.
For applications that require a display buffer small-
er than 38,400 bytes, the on-chip SRAM can be
used as the frame buffer.
The width of the boot device can be chosen by se-
lecting values of PE[1] and PE[0] during power on
reset. These inputs are latched by the rising edge of
nPOR to select the boot option.
PE[1]
0
0
1
1
PE[0]
0
1
0
1
Boot Block
(nCS0)
32-bit
8-bit
16-bit
Undefined
Table 14. Boot Options
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DS453PP2