EP7209 Datasheet, PDF (8/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
7.3 Debug/ICE Test Mode .................................................................................................... 107
7.4 Hi-Z (System) Test Mode ............................................................................................... 107
7.5 Software Selectable Test Functionality .......................................................................... 107
8. PIN INFORMATION .............................................................................................................. 108
8.1 208-Pin LQFP Pin Diagram ............................................................................................. 108
8.2 208-Pin LQFP Numeric Pin Listing ................................................................................. 109
8.3 256-Pin PBGA Pin Diagram ............................................................................................ 112
8.4 256-Ball PBGA Ball Listing .............................................................................................. 113
8.4.1 PBGA Ground Connections ................................................................................... 116
9. PACKAGE SPECIFICATIONS ............................................................................................. 117
9.1 208-Pin LQFP Package Outline Drawing ....................................................................... 117
9.2 EP7209 256-Ball PBGA (17 × 17 × 1.53-mm Body) Dimensions .................................. 118
10. ORDERING INFORMATION ............................................................................................... 119
11. APPENDIX A: BOOT CODE .............................................................................................. 120
12. INDEX ................................................................................................................................. 125
LIST OF FIGURES
Figure 1. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram............................................. 12
Figure 2. EP7209 Block Diagram .................................................................................................. 19
Figure 3. State Diagram ................................................................................................................ 20
Figure 4. CLKEN Timing Entering the Standby State ................................................................... 25
Figure 5. CLKEN Timing Entering the Standby State ................................................................... 25
Figure 6. Codec Interrupt Timing................................................................................................... 36
Figure 7. DAI Interface .................................................................................................................. 37
Figure 8. EP7209 Rev C - Digital Audio Interface Timing – MSB/Left Justified format ................ 38
Figure 9. SSI2 Port Directions in Slave and Master Mode ............................................................ 40
Figure 10. Residual Byte Reading................................................................................................. 42
Figure 11. Video Buffer Mapping................................................................................................... 45
Figure 12. A Maximum EP7209 Based System ............................................................................ 49
Figure 13. Consecutive Memory Read Cycles with Minimum Wait States.................................... 97
Figure 14. Sequential Page Mode Read Cycles with Minimum Wait States ................................. 98
Figure 15. Consecutive Memory Write Cycles with Minimum Wait States .................................... 99
Figure 16. LCD Controller Timings.............................................................................................. 100
Figure 17. SSI Interface for AD7811/2 ........................................................................................ 100
Figure 18. SSI Timing Interface for MAX148/9............................................................................ 101
Figure 19. SSI2 Interface Timings............................................................................................... 101
Figure 20. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram......................................... 108
Figure 21. 256-Ball Plastic Ball Grid Array Diagram ................................................................... 112
LIST OF TABLES
Table 1. Acronyms and Abbreviations........................................................................................... 10
Table 2. Unit of Measurement ....................................................................................................... 11
Table 3. Pin Description Conventions ........................................................................................... 11
Table 4. External Signal Functions................................................................................................ 13
Table 5. SSI/Codec/DAI Pin Multiplexing ...................................................................................... 16
Table 6. Output Bi-Directional Pins ............................................................................................... 17
Table 7. Peripheral Status in Different Power Management States .............................................. 21
Table 8. Exception Priority Handling ............................................................................................. 26
Table 9. Interrupt Allocation in the First Interrupt Register............................................................ 27
Table 10. Interrupt Allocation in the Second Interrupt Register..................................................... 27
Table 11. Interrupt Allocation in the Third Interrupt Register......................................................... 27
Table 12. External Interrupt Source Latencies .............................................................................. 29
Table 13. Chip Select Address Ranges After Boot From On-Chip Boot ROM.............................. 29
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