EP7209 Datasheet, PDF (6/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
3.14.1 Characteristics of the Real Time Clock Interface ................................................... 46
3.15 Dedicated LED Flasher ................................................................................................... 47
3.16 Two PWM Interfaces ....................................................................................................... 47
3.17 Boundary Scan ................................................................................................................ 47
3.18 In-Circuit Emulation ......................................................................................................... 48
3.18.1 Introduction ............................................................................................................ 48
3.18.2 Functionality ........................................................................................................... 48
3.19 Maximum EP7209-Based System .................................................................................. 48
4. MEMORY MAP ....................................................................................................................... 50
5. REGISTER DESCRIPTIONS .................................................................................................. 51
5.1 Internal Registers .............................................................................................................. 51
5.1.1 PADR Port A Data Register ..................................................................................... 54
5.1.2 PBDR Port B Data Register ..................................................................................... 54
5.1.3 PDDR Port D Data Register .................................................................................... 54
5.1.4 PADDR Port A Data Direction Register ................................................................... 54
5.1.5 PBDDR Port B Data Direction Register ................................................................... 54
5.1.6 PDDDR Port D Data Direction Register ................................................................... 55
5.1.7 PEDR Port E Data Register ..................................................................................... 55
5.1.8 PEDDR Port E Data Direction Register ................................................................... 55
5.2 SYSTEM Control Registers ............................................................................................... 56
5.2.1 SYSCON1 The System Control Register 1 ............................................................. 56
5.2.2 SYSCON2 System Control Register 2 ..................................................................... 59
5.2.3 SYSCON3 System Control Register 3 ..................................................................... 61
5.2.4 SYSFLG1 — The System Status Flags Register .................................................... 62
5.2.5 SYSFLG2 System Status Register 2 ....................................................................... 64
5.3 Interrupt Registers ............................................................................................................. 65
5.3.1 INTSR1 Interrupt Status Register 1 ......................................................................... 65
5.3.2 INTMR1 Interrupt Mask Register 1 .......................................................................... 67
5.3.3 INTSR2 Interrupt Status Register 2 ......................................................................... 67
5.3.4 INTMR2 Interrupt Mask Register 2 .......................................................................... 68
5.3.5 INTSR3 Interrupt Status Register 3 ......................................................................... 68
5.3.6 INTMR3 Interrupt Mask Register 3 .......................................................................... 68
5.4 Memory Configuration Registers ....................................................................................... 69
5.4.1 MEMCFG1 Memory Configuration Register 1 ......................................................... 69
5.4.2 MEMCFG2 Memory Configuration Register 2 ......................................................... 69
5.5 Timer/Counter Registers ................................................................................................... 71
5.5.1 TC1D Timer Counter 1 Data Register ..................................................................... 71
5.5.2 TC2D Timer Counter 2 Data Register ..................................................................... 71
5.5.3 RTCDR Real Time Clock Data Register .................................................................. 71
5.5.4 RTCMR Real Time Clock Match Register ............................................................... 71
5.6 LEDFLSH Register ............................................................................................................ 72
5.7 PMPCON Pump Control Register ..................................................................................... 73
5.8 CODR — The CODEC Interface Data Register ................................................................ 74
5.9 UART Registers ................................................................................................................ 74
5.9.1 UARTDR1–2 UART1–2 Data Registers .................................................................. 74
5.9.2 UBRLCR1–2 UART1–2 Bit Rate and Line Control Registers .................................. 75
5.10 LCD Registers ................................................................................................................. 77
5.10.1 LCDCON — The LCD Control Register ................................................................. 77
5.10.2 PALLSW Least Significant Word — LCD Palette Register .................................... 78
5.10.3 PALMSW Most Significant Word — LCD Palette Register .................................... 78
5.10.4 FBADDR LCD Frame Buffer Start Address ........................................................... 79
5.11 SSI Register .................................................................................................................... 79
5.11.1 SYNCIO Synchronous Serial ADC Interface Data Register .................................. 79
5.12 STFCLR Clear all ‘Start Up Reason’ flags location ......................................................... 80
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DS453PP2