EP7209 Datasheet, PDF (23/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
NOTE: The keyboard interrupt is NOT deglitched.
3.3 Resets
There are three asynchronous resets to the EP7209:
nPOR, nPWRFL and nURESET. If any of these are
active, a system reset is generated internally. This
will reset all internal registers in the EP7209 except
the RTC data and match registers. These registers
are only cleared by nPOR allowing the system time
to be preserved through a user reset or power fail
condition.
Any reset will also reset the CPU and cause it to
start execution at the reset vector when the EP7209
returns to the Operating State.
Internal to the EP7209, three different signals are
used to reset storage elements. These are nPOR,
nSYSRES and nSTBY. nPOR is an external signal.
nSTBY is equivalent to the external RUN signal.
nPOR (Power On Reset, active low) is the highest
priority reset signal. When active (low), it will reset
all storage elements in the EP7209. nPOR active
forces nSYSRES and nSTBY active. nPOR will
only be active after the EP7209 is first powered up
and not during any other resets. nPOR active will
clear all flags in the status register except for the
cold reset flag (CLDFLG) bit, which is set.
nSYSRES (System Reset, active low) is generated
internally to the EP7209 if nPOR, nPWRFL or
nURESET are active. It is the second highest prior-
ity reset signal, used to asynchronously reset most
internal registers in the EP7209. nSYSRES active
forces nSTBY and RUN low. nSYSRES is used to
reset the EP7209 and force it into the Standby State
with no co-operation from software. The CPU is
also reset.
The nSTBY and RUN signals are high when the
EP7209 is in the Operating or Idle States and low
when in the Standby State. The main system clock
is valid when nSTBY is high. The nSTBY signal
will disable any peripheral block that is clocked
from the master clock source (i.e., everything ex-
cept for the RTC). In general, a system reset will
clear all registers and nSTBY will disable all pe-
ripherals that require a main clock. The following
peripherals are always disabled by a low level on
nSTBY: two UARTs and IrDA SIR encoder, timer
counters, telephony codec, and the two SSI inter-
faces. In addition, when in the Standby State, the
LCD controller and PWM drive are also disabled.
When operating from an external 13 MHz oscilla-
tor which has become disabled in the Standby State
by using the CLKEN signal (i.e., with CLKENSL
= 0), the oscillator must be stable within 0.125 sec
from the rising edge of the CLKEN signal.
3.4 Clocks
There are two clocking modes for the EP7209. Ei-
ther an external clock input can be used or the on-
chip PLL. The clock source is selected by a strap-
ping option on Port E, pin 2 (PE[2]). If PE[2] is
high at the rising edge of nPOR (i.e., upon power-
up), the external clock mode is selected. If PE[2] is
low, then the on-chip PLL mode is selected. After
power-up, PE[2] can be used as a GPIO.
The EP7209 device contains several separate sec-
tions of logic, each clocked according to its own
clock frequency requirements. When the EP7209 is
in external clock mode, the actual frequencies at
the peripherals will be different than when in PLL
mode. See each peripheral device section for more
details. The section below describes the clocking
for both the ARM720T and address/data bus.
3.4.1 On-Chip PLL
The ARM720T clock can be programmed to
18.432 MHz, 36.864 MHz, 49.152 MHz or
73.728 MHz with the PLL running at twice the
highest possible CPU clock frequency
(147.456 MHz). The PLL uses an external
3.6864 MHz crystal. By chip default, the on-chip
PLL is used and configured such that the
ARM720T and address/data buses run at
18.432 MHz.
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