EP7209 Datasheet, PDF (90/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.16.3.4 Left Channel Receive FIFO Service Request Flag (LCRS)
The left channel receive FIFO service request flag (LCRS) is a read-only bit which is set when the left
channel receive FIFO is nearly filled and requires service to prevent an overrun. LCRS is set any time
the left channel receive FIFO has six or more entries of valid data (half full or more), and cleared when
it has five or fewer (less than half full) entries of data. When the LCRS bit is set, an interrupt request
is made unless the left channel receive FIFO interrupt request mask (LCRM) bit is cleared. After six
or more entries are removed from the receive FIFO, the LCRS flag (and the service request and/or
interrupt) is automatically cleared.
5.16.3.5 Right Channel Transmit FIFO Underrun Status (RCTU)
The right channel transmit FIFO underrun status bit (RCTU) is set when the right channel transmit
logic attempts to fetch data from the FIFO after it has been completely emptied. When an underrun
occurs, the right channel transmit logic continuously transmits the last valid right channel value which
was transmitted before the underrun occurred. Once data is placed in the FIFO and it is transferred
down to the bottom, the right channel transmit logic uses the new value within the FIFO for transmis-
sion. When the RCTU bit is set, an interrupt request is made.
5.16.3.6 Right Channel Receive FIFO Overrun Status (RCRO)
The right channel receive FIFO overrun status bit (RCRO) is set when the right channel receive logic
attempts to place data into the right channel receive FIFO after it has been completely filled. Each
time a new piece of data is received, the set signal to the RCRO status bit is asserted, and the newly
received data is discarded. This process is repeated for each new sample received until at least one
empty FIFO entry exists. When the RCRO bit is set, an interrupt request is made.
5.16.3.7 Left Channel Transmit FIFO Underrun Status (LCTU)
The left channel transmit FIFO underrun status bit (LCTU) is set when the left channel transmit logic
attempts to fetch data from the FIFO after it has been completely emptied. When an underrun occurs,
the left channel transmit logic continuously transmits the last valid left channel value which was trans-
mitted before the underrun occurred. Once data is placed in the FIFO and it is transferred down to the
bottom, the left channel transmit logic uses the new value within the FIFO for transmission. When the
LCTU bit is set, an interrupt request is made.
5.16.3.8 Left Channel Receive FIFO Overrun Status (LCRO)
The left channel receive FIFO overrun status bit (LCRO) is set when the left channel receive logic
places data into the left channel receive FIFO after it has been completely filled. Each time a new
piece of data is received, the set signal to the LCRO status bit is asserted, and the newly received
sample is discarded. This process is repeated for each new piece of data received until at least one
empty FIFO entry exists. When the LCRO bit is set, an interrupt request is made.
5.16.3.9 Right Channel Transmit FIFO Not Full Flag (RCNF)
The right channel transmit FIFO not full flag (RCNF) is a read-only bit which is set whenever the right
channel transmit FIFO contains one or more entries which do not contain valid data and is cleared
when the FIFO is completely full. This bit can be polled when using programmed I/O to fill the right
channel transmit FIFO. This bit does not request an interrupt.
5.16.3.10 Right Channel Receive FIFO Not Empty Flag (RCNE)
The right channel receive FIFO not empty flag (RCNELCNF) is a read-only bit which is set when ever
the right channel receive FIFO contains one or more entries of valid data and is cleared when it no
longer contains any valid data. This bit can be polled when using programmed I/O to remove remain-
ing data from the receive FIFO. This bit does not request an interrupt.
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