EP7209 Datasheet, PDF (67/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.3.2 INTMR1 Interrupt Mask Register 1
ADDRESS: 0x8000.0280
15
SSEOTI
7
EINT3
14
UMSINT
6
EINT2
13
URXINT
5
EINT1
12
UTXINT
4
CSINT
11
TINT
3
MCINT
10
RTCMI
2
WEINT
9
TC2OI
1
BLINT
8
TC1OI
0
EXTFIQ
5.3.3
This interrupt mask register is a 32-bit read/write register, which is used to selectively enable any of
the first 16 interrupt sources within the EP7209. The four shaded interrupts all generate a fast interrupt
request to the ARM720T processor (FIQ), this will cause a jump to processor virtual address
0000.0001C. All other interrupts will generate a standard interrupt request (IRQ), this will cause a
jump to processor virtual address 0000.00018. Setting the appropriate bit in this register enables the
corresponding interrupt. All bits are cleared by a system reset. Please refer to INTSR1 Interrupt Sta-
tus Register 1 for individual bit details.
INTSR2 Interrupt Status Register 2
ADDRESS: 0x8000.1240
15:14
Reserved
13
URXINT2
12
UTXINT2
11:3
Reserved
2
SS2TX
1
SS2RX
0
KBDINT
This register is an extension of INTSR1, containing status bits for backward compatibility with CL-
PS7111. The interrupt status register also reflects the current state of the new interrupt sources within
the EP7209. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given in
Table 33.
Bit
0
1
2
12
Description
KBDINT: Keyboard interrupt. This interrupt is generated whenever a key is pressed, from the log-
ical OR of the first 6 or all 8 of the Port A inputs (depending on the state of the KBD6 bit in the
SYSCON2 register. The interrupt request is latched, and can be de-asserted by writing to the
KBDEOI location.
NOTE: KBDINT is not deglitched.
SS2RX: Synchronous serial interface 2 receive FIFO half or greater full interrupt. This is gener-
ated when RX FIFO contains 8 or more half-words. This interrupt is cleared only when the RX
FIFO is emptied or one SSI2 clock after RX is disabled.
SS2TX: Synchronous serial interface 2 transmit FIFO less than half empty interrupt. This is gen-
erated when TX FIFO contains fewer than 8 byte pairs. This interrupt gets cleared by loading the
FIFO with more data or disabling the TX. One synchronization clock required when disabling the
TX side before it takes effect.
UTXINT2: UART2 transmit FIFO half empty interrupt. The function of this interrupt source
depends on whether the UART2 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is clear in
the UART2 bit rate and line control register), this interrupt will be active when there is no data in
the UART2 TX data holding register and be cleared by writing to the UART2 data register. If the
FIFO is enabled this interrupt will be active when the UART2 TX FIFO is half or more empty, and
is cleared by filling the FIFO to at least half full.
DS453PP2
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