EP7209 Datasheet, PDF (15/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
Function
ADC
Interface
(SSI1)
IrDA and
RS232
Interfaces
LCD
Keyboard &
Buzzer drive
LED Flasher
General
Purpose I/O
PWM
Drives
Signal
Name
ADCCLK
nADCCS
ADCOUT
ADCIN
SMPCLK
LEDDRV
PHDIN
TXD[1:2]
RXD[1:2]
DSR
DCD
CTS
DD[0:3]
CL[1]
CL[2]
FRM
M
COL[0:7]
BUZ
PD[0]/
LEDFLSH
PA[0:7]
PB[0]/PRDY1
PB[1]/PRDY2
PB[2:7]
PD[0:7]
PE[0]/
BOOTSEL[0]
PE[1]/
BOOTSEL[1]
PE[2]/
CLKSEL
DRIVE[0:1]
FB[0:1]
Signal
Description
O Serial clock output
O Chip select for ADC interface
O Serial data output
I Serial data input
O Sample clock output
O Infrared LED drive output (UART1)
I Photo diode input (UART1)
O RS232 UART1 and 2 TX outputs
I RS232 UART1 and 2 RX inputs
I RS232 DSR input
I RS232 DCD input
I RS232 CTS input
I/O
LCD serial display data; pins can be used on power up to read the ID of some
LCD modules (See Table 6).
O LCD line clock
O LCD pixel clock
O LCD frame synchronization pulse output
O LCD AC bias drive
O Keyboard column drives (SYSCON1)
O Buzzer drive output (SYSCON1)
O
LED flasher driver — multiplexed with Port D bit 0. This pin can provide up to
4 mA of drive current.
I/O
Port A I/O (bit 6 for boot clock option, bit 7 for CL-PS6700 PRDY input); also
used as keyboard row inputs
Port B I/O. All eight Port B bits can be used as GPIOs.
When the PC CARD1 or 2 control bits in the SYSCON2 register are de-
I/O asserted, PB[0] and PB[1] are available for GPIO. When asserted, these port
bits are used as the PRDY signals for connected CL-PS6700 PC Card Host
Adapter devices.
I/O Port D I/O
I/O
Port E I/O (3 bits only). Can be used as general purpose I/O during normal
operation.
During power-on reset, PE[0] and PE[1] are inputs and are latched by the ris-
I/O ing edge of nPOR to select the memory width that the EP7209 will use to read
from the boot code storage device (i.e., external 8-bit-wide FLASH bank).
During power-on reset, PE[2] is latched by the rising edge of nPOR to select
I/O the clock mode of operation (i.e., either the PLL or external 13 MHz clock
mode).
PWM drive outputs. These pins are inputs on power up to determine what
I/O polarity the output of the PWM should be when active. Otherwise, these pins
are always an output (See Table 6).
I PWM feedback inputs
Table 4. External Signal Functions (cont.)
DS453PP2
15