EP7209 Datasheet, PDF (68/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
Bit
13
Description
URXINT2: UART2 receive FIFO half full interrupt. The function of this interrupt source depends
on whether the UART2 FIFO is enabled. If the FIFO is disabled this interrupt will be active when
there is valid RX data in the UART2 RX data holding register and be cleared by reading this data.
If the FIFO is enabled this interrupt will be active when the UART2 RX FIFO is half or more full or
if the FIFO is non empty and no more characters have been received for a three character time
out period. It is cleared by reading all the data from the RX FIFO.
Table 33. INSTR2 (cont.)
5.3.4 INTMR2 Interrupt Mask Register 2
ADDRESS: 0x8000.1280
15:14
Reserved
13
URXINT2
12
UTXINT2
11:3
Reserved
2
SS2TX
1
SS2RX
0
KBDINT
5.3.5
This register is an extension of INTMR1, containing interrupt mask bits for the backward compatibility
with the CL-PS7111. Please refer to INTSR2 for individual bit details.
INTSR3 Interrupt Status Register 3
ADDRESS: 0x8000.2240
7:1
Reserved
0
DAIINT
This register is an extension of INTSR1 and INTSR2 containing status bits for the new features of the
EP7209. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given in
Table 34.
Bit
0
Description
MCPINT: DAI interface interrupt. The cause must be determined by reading the DAI status regis-
ter. It is mapped to the FIQ interrupt on the ARM720T processor
Table 34. INTSR3
5.3.6 INTMR3 Interrupt Mask Register 3
ADDRESS: 0x8000.2280
7:1
Reserved
0
DAIINT
This register is an extension of INTMR1 and INTMR2, containing interrupt mask bits for the new fea-
tures of the EP7209. Please refer to INTSR3 for individual bit details.
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