EP7209 Datasheet, PDF (87/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.16.2 DAI Data Registers
The DAI contains three data registers: DAIDR0 addresses the top entry of the right channel transmit FIFO
and bottom entry of the right channel receive FIFO; DAIDR1 addresses the top and bottom entry of the
left channel transmit and receive FIFOs, respectively; and DAIDR2 is used to perform enable and disable
the DAI FIFOs.
5.16.2.1 DAI Data Register 0
ADDRESS: 0x8000.2040
31:16
Reserved
31:16
Reserved
15:0
Bottom of Right Channel Receive FIFO
Read Access
15:0
Top of Right Channel Transmit FIFO
Write Access
When DAI Data Register 0 (DAIDR0) is read, the bottom entry of the right channel receive FIFO is
accessed. As data is removed by the DAI’s receive logic from the incoming data frame, it is placed
into the top entry of the right channel receive FIFO and is transferred down an entry at a time until it
reaches the last empty location within the FIFO. Data is removed by reading DAIDR0, which accesses
the bottom entry of the right channel FIFO. After DAIDR0 is read, the bottom entry is invalidated, and
all remaining values within the FIFO automatically transfer down one location.
When DAIDR0 is written, the top-most entry of the right channel transmit FIFO is accessed. After a
write, data is automatically transferred down to the lowest location within the transmit FIFO which
does not already contain valid data. Data is removed from the bottom of the FIFO one value at a time
by the transmit logic, loaded into the correct position within the 64-bit transmit serial shifter, then se-
rially shifted out onto the SDOUT pin.
Table 49 shows DAIDR0. Note that the transmit and receive right channel FIFOs are cleared when
the device is reset, or by writing a zero to DAIEN (DAI disabled). Also, note that writes to reserved
bits are ignored and reads return zeros.
Bit
0:15
16:31
Description
RIGHT CHANNEL DATA: Transmit/Receive right channel FIFO Data
Read — Bottom of Right Channel Receive FIFO data
Write — Top of Right Channel Transmit FIFO data
Reserved
Table 49. DAI Data Register 0
DS453PP2
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