EP7209 Datasheet, PDF (5/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
EP7209
TABLE OF CONTENTS
1. CONVENTIONS ...................................................................................................................... 10
1.1 Acronyms and Abbreviations ............................................................................................ 10
1.2 Units of Measurement ...................................................................................................... 11
1.3 General Conventions ........................................................................................................ 11
1.4 Pin Description Conventions ............................................................................................. 11
2. PIN INFORMATION ................................................................................................................ 12
2.1 208-Pin LQFP Pin Diagram .............................................................................................. 12
2.2 Pin Descriptions ................................................................................................................ 13
2.2.1 External Signal Functions ................................................................................... 13
2.2.2 SSI/Codec/DAI Pin Multiplexing ............................................................................ 16
2.2.3 Output Bi-Directional Pins .................................................................................... 17
3. FUNCTIONAL DESCRIPTION ............................................................................................... 18
3.1 CPU Core .......................................................................................................................... 19
3.2 State Control ..................................................................................................................... 20
3.2.1 Standby State .......................................................................................................... 20
3.2.1.1 UART in Standby State ............................................................................... 21
3.2.2 Idle State ................................................................................................................. 22
3.2.3 Keyboard Interrupt ................................................................................................... 22
3.3 Resets ............................................................................................................................... 23
3.4 Clocks ............................................................................................................................... 23
3.4.1 On-Chip PLL ............................................................................................................ 23
3.4.1.1 Characteristics of the PLL Interface ............................................................ 24
3.4.2 External Clock Input (13 MHz) ................................................................................ 24
3.4.3 Dynamic Clock Switching When in the PLL Clocking Mode .................................... 26
3.5 Interrupt Controller ............................................................................................................ 26
3.5.1 Interrupt Latencies in Different States ..................................................................... 28
3.5.1.1 Operating State ........................................................................................... 28
3.5.1.2 Standby State .............................................................................................. 28
3.6 EP7209 Boot ROM .......................................................................................................... 29
3.7 Memory and I/O Expansion Interface ............................................................................... 30
3.8 CL-PS6700 PC Card Controller Interface ......................................................................... 31
3.9 Endianness ....................................................................................................................... 33
3.10 Internal UARTs (Two) and SIR Encoder ......................................................................... 34
3.11 Serial Interfaces .............................................................................................................. 34
3.11.1 Codec Sound Interface .......................................................................................... 36
3.11.2 Digital Audio Interface ........................................................................................... 37
3.11.2.1 DAI Operation ............................................................................................ 38
3.11.2.2 DAI Frame Format ..................................................................................... 38
3.11.2.3 DAI Signals ................................................................................................ 38
3.11.3 ADC Interface — Master Mode Only SSI1 (Synchronous Serial Interface) .......... 39
3.11.4 Master/Slave SSI2 (Synchronous Serial Interface 2) ........................................... 39
3.11.4.1 Read Back of Residual Data ..................................................................... 42
3.11.4.2 Support for Asymmetric Traffic .................................................................. 42
3.11.4.3 Continuous Data Transfer ......................................................................... 43
3.11.4.4 Discontinuous Clock .................................................................................. 43
3.11.4.5 Error Conditions ........................................................................................ 43
3.11.4.6 Clock Polarity ............................................................................................ 43
3.12 LCD Controller with Support for On-Chip Frame Buffer .................................................. 43
3.13 Timer Counters ............................................................................................................... 45
3.13.1 Free Running Mode ............................................................................................... 46
3.13.2 Prescale Mode ...................................................................................................... 46
3.14 Real Time Clock .............................................................................................................. 46
DS453PP2
DS453PP2
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