EP7209 Datasheet, PDF (69/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.4 Memory Configuration Registers
5.4.1 MEMCFG1 Memory Configuration Register 1
ADDRESS: 0x8000.0180
31:24
nCS[3] configuration
23:16
nCS[2] configuration
15:8
nCS[1] configuration
7:0
nCS[0] configuration
Expansion and ROM space is selected by one of eight chip selects. One of the chip selects (nCS[6])
is used internally for the on-chip SRAM, and the configuration is hardwired for 32-bit wide, minimum
wait state operation. nCS[7] is used for the on-chip Boot ROM and the configuration field is hardwired
for 8-bit wide, minimum wait state operation. Data written to the configuration fields for either nCS[6]
or nCS7 will be ignored. Two of the chip selects (nCS[4:5]) can be used to access two CL-PS6700
PC CARD controller devices, and when either of these interfaces is enabled, the configuration field
for the appropriate chip select in the MEMCFG2 register is ignored. When the PC CARD1 or 2 control
bit in the SYSCON2 register is disabled, then nCS[4] and nCS[5] are active as normal and can be
programmed using the relevant fields of MEMCFG2, as for the other four chip selects. All of the six
external chip selects are active for 256 Mbytes and the timing and bus transfer width can be pro-
grammed individually. This is accomplished by programming the six byte-wide fields contained in two
32-bit registers, MEMCFG1 and MEMCFG2. All bits in these registers are cleared by a system reset
(except for the nCS[6] and nCS[7] configurations).
The Memory Configuration Register 1 is a 32-bit read/write register which sets the configuration of
the four expansion and ROM selects nCS[0:3]. Each select is configured with a 1-byte field starting
with expansion select 0.
5.4.2 MEMCFG2 Memory Configuration Register 2
ADDRESS: 0x8000.01C0
31:24
(Boot ROM)
7
CLKENB
23:16
(Local SRAM)
6
SQAEN
15:8
nCS[5] configuration
5:2
Wait States Field
7:0
nCS[4] configuration
1:0
Bus width
The Memory Configuration Register 2 is a 32-bit read/write register which sets the configuration of
the two expansion and ROM selects nCS[4:5]. Each select is configured with a 1-byte field starting
with expansion select 4.
Each of the six non-reserved byte fields for chip select configuration in the memory configuration reg-
isters are identical and define the number of wait states, the bus width, enable EXPCLK output during
accesses and enable sequential mode access. This byte field is defined below. This arrangement ap-
plies to nCS[0:3], and nCS[4:5] when the PC CARD enable bits in the SYSCON2 register are not set.
The state of these bits is ignored for the Boot ROM and local SRAM fields in the MEMCFG2 register.
Table 35 defines the bus width field. Note that the effect of this field is dependent on the two BOOTBIT
bits that can be read in the SYSFLG1 register. All bits in the memory configuration register are cleared
by a system reset and the state of the BOOTBIT bits are determined by Port E bits 0 and 1 on the
EP7209 during power-on reset. The state of PE[1] and PE[0] determine whether the EP7209 is going
to boot from either 32-bit wide, 16-bit wide or 8-bit wide ROMs.
Table 36 shows the values for the wait states for random and sequential wait states at 13 and 18 MHz
bus rates. At 36 MHz bus rate, the encoding becomes more complex. Table 37 preserves compati-
bility with the previous devices, while allowing the previously unused bit combinations to specify more
variations of random and sequential wait states.
DS453PP2
69