EP7209 Datasheet, PDF (56/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.2 SYSTEM Control Registers
5.2.1 SYSCON1 The System Control Register 1
ADDRESS: 0x8000.0100
23
15
SIREN
7
TC2S
22
14
CDENRX
6
TC2M
21
13
CDENTX
5
TC1S
20
IRTXM
12
LCDEN
4
TC1M
19
WAKEDIS
11
DBGEN
3:0
Keyboard scan
The system control register is a 21-bit read/write register which controls all the general configuration
of the EP7209, as well as modes etc. for peripheral devices. All bits in this register are cleared by a
system reset. The bits in the system control register SYSCON1 are defined in Table 27.
Bit
0:3
4
5
6
7
8
Description
Keyboard scan: This 4-bit field defines the state of the keyboard column drives. The following
table defines these states.
Keyboard Scan
0
1
2–7
8
9
10
11
12
13
14
15
Column
All driven high
All driven low
All high impedance (tristate)
Column 0 only driven high all others high impedance
Column 1 only driven high all others high impedance
Column 2 only driven high all others high impedance
Column 3 only driven high all others high impedance
Column 4 only driven high all others high impedance
Column 5 only driven high all others high impedance
Column 6 only driven high all others high impedance
Column 7 only driven high all others high impedance
TC1M: Timer counter 1 mode. Setting this bit sets TC1 to prescale mode, clearing it sets free run-
ning mode.
TC1S: Timer counter 1 clock source. Setting this bit sets the TC1 clock source to 512 kHz, clear-
ing it sets the clock source to 2 kHz.
TC2M: Timer counter 2 mode. Setting this bit sets TC2 to prescale mode, clearing it sets free run-
ning mode.
TC2S: Timer counter 2 clock source. Setting this bit sets the TC2 clock source to 512 kHz, clear-
ing it sets the clock source to 2 kHz.
UART1EN: Internal UART enable bit. Setting this bit enables the internal UART.
Table 27. SYSCON1
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