EP7209 Datasheet, PDF (85/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
Bit
23
24:31
Description
LBM: Loop Back Mode
0 — Normal serial port operation enabled
1 — Output of serial shifter is connected to input of serial shifter internally and control of SDIN,
SDOUT, SCLK, and LRCK pins is given to the PPC unit.
Reserved
Table 48. DAI Control Register (cont.)
5.16.1.1 DAI Enable (DAIEN)
The DAI enable (DAIEN) bit is used to enable and disable all DAI operation.
When the DAI is disabled, all of its clocks are powered down to minimize power consumption. Note
that DAIEN is the only control bit within the DAI interface that is reset to a known state. It is cleared
to zero to ensure the DAI timing is disabled following a reset of the device.
When the DAI timing is enabled, SCLK begins to transition and the start of the first frame is signaled
by driving the LRCK pin low. The rising and falling-edge of LRCK coincides with the rising and falling-
edge of SCLK. As long as the DAIEN bit is set, the DAI interface operates continuously, transmitting
and receiving 128 bit data frames. When the DAIEN bit is cleared, the DAI interface is disabled im-
mediately, causing the current frame which is being transmitted to be terminated. Clearing DAIEN re-
sets the DAI’s interface FIFOs. However DAI data register 3, the control register and the status
register are not reset. Therefore, the user must ensure these registers are properly reconfigured be-
fore re-enabling the DAI interface.
5.16.1.2 DAI Interrupt Generation
The DAI interface can generate four maskable interrupts and four non-maskable interrupts, as de-
scribed in the sections below. Only one interrupt line is wired into the interrupt controller for the whole
DAI interface. This interrupt is the wired OR of all eight interrupts (after masking where appropriate).
The software servicing the interrupts must read the status register in the DAI to determine which
source(s) caused the interrupt. It is possible to prevent any DAI sources causing an interrupt by mask-
ing the DAI interrupt in the interrupt controller register.
5.16.1.3 Left Channel Transmit FIFO Interrupt Mask (LCTM)
The left channel sample transmit FIFO interrupt mask (LCTM) bit is used to mask or enable the left
channel sample transmit FIFO service request interrupt. When LATM = 0, the interrupt is masked and
the state of the left channel transmit FIFO service request (LCTS) bit within the DAI status register is
ignored by the interrupt controller. When LCTM = 1, the interrupt is enabled and whenever LCTS is
set (one) an interrupt request is made to the interrupt controller. Note that programming LCTM = 0
does not affect the current state of LCTS or the left channel transmit FIFO logic’s ability to set and
clear LCTS; it only blocks the generation of the interrupt request.
5.16.1.4 Left Channel Receive FIFO Interrupt Mask (LARM)
The left channel sample receive FIFO interrupt mask (LCRM) bit is used to mask or enable the left
channel receive FIFO service request interrupt. When LCRM = 0, the interrupt is masked and the
state of the left channel sample receive FIFO service request (LCRS) bit within the DAI status register
is ignored by the interrupt controller. When LCRM = 1, the interrupt is enabled and whenever LCRS
is set (one) an interrupt request is made to the interrupt controller. Note that programming LCRM = 0
does not affect the current state of LCRS or the left channel receive FIFO logic’s ability to set and
clear LCRS, it only blocks the generation of the interrupt request.
DS453PP2
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