EP7209 Datasheet, PDF (74/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
5.8 CODR — The CODEC Interface Data Register
ADDRESS: 0x8000.0440
The CODR register is an 8-bit read/write register, to be used with the codec interface. This is selected
by the appropriate setting of bit 0 (SERSEL) of the SYSCON2 register. Data written to or read from
this register is pushed or popped onto the appropriate 16-byte FIFO buffer. Data from this buffer is
then serialized and sent to or received from the codec sound device. When the codec is enabled, the
codec interrupt CSINT is generated repetitively at 1/8th of the byte transfer rate and the state of the
FIFOs can be read in the system flags register. The net data transfer rate to/from the codec device is
8 kBytes/s, giving an interrupt rate of 1 kHz.
5.9 UART Registers
5.9.1 UARTDR1–2 UART1–2 Data Registers
ADDRESS: 0x8000.0480 and 0x8000.1480
10
OVERR
9
PARERR
8
FRMERR
7:0
RX data
The UARTDR registers are 11-bit read and 8-bit write registers for all data transfers to or from the
internal UARTs 1 and 2.
Data written to these registers is pushed onto the 16-byte data TX holding FIFO if the FIFO is enabled.
If not it is stored in a one byte holding register. This write will initiate transmission from the UART.
The UART data read registers are made up of the 8-bit data byte received from the UART together
with three bits of error status. If the FIFO is enabled, data read from this register is popped from the
16 byte data RX FIFO. If the FIFO is not enabled, it is read from a one byte buffer register containing
the last byte received by the UART. If it is enabled, data received and error status is automatically
pushed onto the RX FIFO. The RX FIFO is 10-bits wide by 16 deep.
NOTE: These registers should be accessed as words.
Bit
8
9
10
Description
FRMERR: UART framing error. This bit is set if the UART detected a framing error while receiv-
ing the associated data byte. Framing errors are caused by non-matching word lengths or bit
rates.
PARERR: UART parity error. This bit is set if the UART detected a parity error while receiving the
data byte.
OVERR: UART over-run error. This bit is set if more data is received by the UART and the FIFO
is full. The overrun error bit is not associated with any single character, and so is not stored in the
FIFO, if this bit is set the entire contents of the FIFO is invalid and should be cleared. This error
bit is cleared by reading the UARTDR register.
Table 43. UARTDR1-2 UART1-2
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