Z8F082ASH020SC Datasheet, PDF (98/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
80
Table 55. Watch-Dog Timer Approximate Time-Out Delays
WDT Reload Value
(Hex)
000004
FFFFFF
WDT Reload Value
(Decimal)
4
16,777,215
Approximate Time-Out Delay
(with 10KHz typical WDT oscillator frequency)
Typical
400 µs
28 minutes
Description
Minimum time-out delay
Maximum time-out delay
Watch-Dog Timer Refresh
When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog
Timer Reload registers. The Watch-Dog Timer counts down to 000000H unless a WDT
instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the
downcounter to be reloaded with the WDT Reload value stored in the Watch-Dog Timer
Reload registers. Counting resumes following the reload operation.
When the Z8 Encore! XP^® F08xA Series devices are operating in DEBUG Mode (using
the On-Chip Debugger), the Watch-Dog Timer is continuously refreshed to prevent any
Watch-Dog Timer time-outs.
Watch-Dog Timer Time-Out Response
The Watch-Dog Timer times out when the counter reaches 000000H. A time-out of the
Watch-Dog Timer generates either an interrupt or a system reset. The WDT_RES Flash
Option Bit determines the time-out response of the Watch-Dog Timer. Refer to the chapter
“Flash Option Bits” on page 138 for information regarding programming of the WDT_RES
Flash Option Bit.
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watch-Dog Timer issues
an interrupt request to the interrupt controller and sets the WDT status bit in the Watch-Dog
Timer Control register. If interrupts are enabled, the eZ8 CPU responds to the interrupt
request by fetching the Watch-Dog Timer interrupt vector and executing code from the
vector address. After time-out and interrupt generation, the Watch-Dog Timer counter
rolls over to its maximum value of FFFFFH and continues counting. The Watch-Dog
Timer counter is not automatically returned to its Reload Value.
The Reset Status Register (page 26) must be read before clearing the WDT interrupt. This
read clears the WDT timeout flag and prevents further WDT interrupts for immediately
occurring.
PS024705-0405
PRELIMINARY
Watch-Dog Timer