Z8F082ASH020SC Datasheet, PDF (85/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
67
1. Write to the Timer Control register to:
– Disable the timer
– Configure the timer for CAPTURE mode.
– Set the prescale value.
– Set the Capture edge (rising or falling) for the Timer Input.
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. Clear the Timer PWM High and Low Byte registers to 0000H. Clearing these
registers allows user software to determine if interrupts were generated by either a
capture event or a reload. If the PWM High and Low Byte registers still contain
0000H after the interrupt, the interrupt was generated by a Reload.
5. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input capture and reload events. If appropriate, configure the timer interrupt to be
generated only at the input capture event or the reload event by setting TICONFIG
field of the TxCTL1 register.
6. Configure the associated GPIO port pin for the Timer Input alternate function.
7. Write to the Timer Control register to enable the timer and initiate counting.
In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated
using the following equation:
Capture Elapsed Time (s) = ⁽---C----a---p----t--u---r---e----V----a---l--u---e----^–-----S---t--a---r---t---V-----a---l-u----e---⁾---^×----^P---^r--^e--^s--^c--^a---^l-^e-
System Clock Frequency (Hz)
CAPTURE RESTART Mode
In CAPTURE RESTART mode, the current timer count value is recorded when the accept-
able external Timer Input transition occurs. The Capture count value is written to the
Timer PWM High and Low Byte Registers. The timer input is the system clock. The
TPOL bit in the Timer Control register determines if the Capture occurs on a rising edge or
a falling edge of the Timer Input signal. When the Capture event occurs, an interrupt is
generated and the count value in the Timer High and Low Byte registers is reset to 0001H
and counting resumes. The INPCAP bit in TxCTL1 register is set to indicate the timer
interrupt is because of an input capture event.
If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001H and counting resumes. The INPCAP bit in TxCTL1 register is cleared to indicate
the timer interrupt is not caused by an input capture event.
PS024705-0405
PRELIMINARY
Timers