Z8F082ASH020SC Datasheet, PDF (131/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
113
Programmable Trigger Point Alarm
The ADC contains two programmable trigger values, a high and a low. Each of these val-
ues is 8 bits and is NOT a two’s complement number. The alarm is intended primarily for
single ended operation and so the alarm values reflect positive numbers only. Both thresh-
olds have independent control and status bits.
When enabled and the ADC bits exceed the high threshold, an ADC interrupt is asserted
and the high threshold status bit is set. When enabled and the ADC bits are less than the
low threshold, an ADC interrupt is asserted and the low threshold status bit is set.
Because the alarm value is positive it is compared to the most significant 8 data bits of the
ADC values, excluding the sign bit. The ADC alarm bits are compared to
{ADCD_H[6:0],ADCD_L[7]}. Alternatively, the alarm value is compared to the ADC
value shifted left by one bit. Negative ADC values never trigger the high alarm and always
trigger the low alarm. Because the ADC output is software compensated for offset, nega-
tive (pre-compensated) values can occur in SINGLE-ENDED mode.
The alarm is used in CONTINUOUS mode, in which it no longer is required to service an
interrupt for each ADC sample. If used in SINGLE-SHOT mode, the ADC never inter-
rupts the CPU unless the single sample triggers an alarm.
The alarm status bits are updated on each conversion, regardless of the alarm enable bit
values. The alarm enable bits only determine whether or not an interrupt is generated.
Interrupts
The ADC is able to interrupt the CPU under three conditions:
• When a conversion has been completed
• When the 8 Most Significant Bits of a sample exceed the programmable high threshold
ADCTHI[7:0]
• When the 8 Most Significant Bits of a sample is less than the programmable low threshold
ADCTLO[7:0]
The conversion interrupt occurs when the ADC is enabled and both alarms are disabled.
When either or both alarms are enabled, the conversion interrupt is disabled and only the
alarm interrupts occur.
When the ADC is disabled, none of the three sources cause an interrupt to be asserted;
however, an interrupt pending when the ADC is disabled is not cleared.
The three interrupt events share a common CPU interrupt. The interrupt service routine
must query the ADC status register to determine the cause of an ADC interrupt. The regis-
ter bits denoting ADC alarm status can only be set by hardware and are cleared by writing
a 1.
PS024705-0405
PRELIMINARY
Analog-to-Digital Converter