Z8F082ASH020SC Datasheet, PDF (73/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
55
BITS
FIELD
RESET
R/W
ADDR
Table 40. IRQ1 Enable Low Bit Register (IRQ1ENL)
7
6
5
PA7ENL PA6CENL PA5ENL
0
0
0
R/W
R/W
R/W
4
3
PA4ENL PA3ENL
0
0
R/W
R/W
FC5H
2
PA2ENL
0
R/W
1
PA1ENL
0
R/W
0
PA0ENL
0
R/W
PA6CENH—Port A Bit[6] or Comparator Interrupt Request Enable Low Bit
PAxENL—Port A Bit[x] Interrupt Request Enable Low Bit
IRQ2 Enable High and Low Bit Registers
Table 41 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg-
isters (Tables 42 and 43) form a priority encoded enabling for interrupts in the Interrupt
Request 2 register. Priority is generated by setting bits in each register.
Table 41. IRQ2 Enable and Priority Encoding
IRQ2ENH[x] IRQ2ENL[x] Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
where x indicates the register bits from 0–7.
BITS
FIELD
RESET
R/W
ADDR
Table 42. IRQ2 Enable High Bit Register (IRQ2ENH)
7
6
5
4
3
2
Reserved
C3ENH C2ENH
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
FC7H
Reserved—Must be 0.
C3ENH—Port C3 Interrupt Request Enable High Bit
C2ENH—Port C2 Interrupt Request Enable High Bit
1
C1ENH
0
R/W
0
C0ENH
0
R/W
PS024705-0405
PRELIMINARY
Interrupt Controller