Z8F082ASH020SC Datasheet, PDF (203/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
185
Assembly
Mnemonic
SWAP dst
TCM dst, src
TCMX dst, src
TM dst, src
TMX dst, src
TRAP Vector
WDT
XOR dst, src
Flags Notation:
Table 116. eZ8 CPU Instruction Summary (Continued)
Symbolic Operation
Address Mode _Opcode(s)
Flags
Fetch Instr.
dst src
(Hex) C Z S V D H Cycles Cycles
dst[7:4] ↔ dst[3:0]
R
F0
X* *X– – 2
2
IR
F1
2
3
(NOT dst) AND src
r
r
62
–**0–– 2
3
r
Ir
63
2
4
R
R
64
3
3
R
IR
65
3
4
R
IM
66
3
3
IR
IM
67
3
4
(NOT dst) AND src
ER ER
68
–**0–– 4
3
ER IM
69
4
3
dst AND src
r
r
72
–**0–– 2
3
r
Ir
73
2
4
R
R
74
3
3
R
IR
75
3
4
R
IM
76
3
3
IR
IM
77
3
4
dst AND src
ER ER
78
–**0–– 4
3
ER IM
79
4
3
SP ← SP – 2
@SP ← PC
SP ← SP – 1
@SP ← FLAGS
PC ← @Vector
Vector
F2
––––– – 2
6
5F
––––– – 1
2
dst ← dst XOR src
r
r
B2
–**0–– 2
3
r
Ir
B3
2
4
R
R
B4
3
3
R
IR
B5
3
4
R
IM
B6
3
3
IR
IM
B7
3
4
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS024705-0405
PRELIMINARY
eZ8 CPU Instruction Set