Z8F082ASH020SC Datasheet, PDF (112/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Seriess
Product Specification
94
Receiver
Ready
Receiver
Interrupt
Read Status
No
Errors?
Yes
Read Data which
clears RDA bit and
resets error bits
Read Data
Discard Data
Figure 14.UART Receiver Interrupt Service Routine Flow
Baud Rate Generator Interrupts
If the Baud Rate Generator (BRG) interrupt enable is set, the UART Receiver interrupt
asserts when the UART Baud Rate Generator reloads. This condition allows the Baud
Rate Generator to function as an additional counter if the UART functionality is not
employed.
UART Baud Rate Generator
The UART Baud Rate Generator creates a lower frequency baud rate clock for data trans-
mission. The input to the Baud Rate Generator is the system clock. The UART Baud Rate
High and Low Byte registers combine to create a 16-bit baud rate divisor value
PS024705-0405
PRELIMINARY
UART