Z8F082ASH020SC Datasheet, PDF (137/244 Pages) Zilog, Inc. – Z8 Encore XP-R F08xA Series with eXtended Peripherals

Z8 Encore! XP^® F08xA Series
Product Specification
119
ADC Control/Status Register 1
The second ADC Control register configures the input buffer stage, enables the threshold
interrupts and contains the status of both threshold triggers.
Table 71. ADC Control/Status Register 1 (ADCCTL1)
BITS
FIELD
RESET
R/W
ADDR
7
6
REFSELH ALMHST
1
0
R/W
R/W
5
ALMLST
0
R/W
4
3
ALMHEN ALMLEN
0
0
R/W
R/W
F71H
2
1
0
BUFMODE[2:0]
0
0
0
R/W
R/W
R/W
REFSELH—Voltage Reference Level Select High Bit; in conjunction with the Low bit
(REFSELL) in ADC Control Register 0, this determines the level of the internal voltage ref-
erence; the following details the effects of {REFSELH, REFSELL}; this reference is inde-
pendent of the Comparator reference
00= Internal Reference Disabled, reference comes from external pin
01= Internal Reference set to 1.0 V
10= Internal Reference set to 2.0 V (default)
11= Reserved
ALMHST—Alarm High Status; this bit can only be set by hardware and must be written
with a 1 to clear
0= No alarm occurred.
1= A high threshold alarm occurred.
ALMLST—Alarm Low Status; this bit can only be set by hardware and must be written
with a 1 to clear
0= No alarm occurred.
1= A low threshold alarm occurred.
ALMHEN—Alarm High Enable
0= Alarm interrupt for high threshold is disabled. The alarm status bit remains set when
the alarm threshold is passed.
1= High threshold alarm interrupt is enabled.
ALMLEN—Alarm Low Enable
0= Alarm interrupt for low threshold is disabled. The alarm status bit remains set when the
alarm threshold is passed.
1= Low threshold alarm interrupt is enabled.
BUFMODE[2:0] - Input Buffer Mode Select
000 = Single-ended, unbuffered input
001 = Single-ended, buffered input with unity gain
010 = Reserved
011 = Reserved
PS024705-0405
PRELIMINARY
Analog-to-Digital Converter